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  • [C/C++] ext_int.rar ... maskable interrupt EXNMI1, EXNMI2, input termination EXINT5 which has small keys, as long as the user press the small button, EXINT5 pin on the emergence of low power ping. As long as the corresponding settings in the software, you can interrupt occurred.
    Category: SCM Upload User:hongonli Size:84K
  • [Others] test2.rar
    Category: .net Upload User:gdwtdg2009 Size:10K
  • [Others] 2005_Using_Hidden_Markov_Model_for_Text_Informatio Based on Maximum Entropy of Hidden Markov Model Text Information Extraction, Ya-Ping Lin! Liu in!廃?first! Chen Zhiping! Cai-jun,
    Category: Algorithm Upload User:liuyisx Size:167K
  • [C/C++] zaixianxiazai.rar Single-chip can be programmed through the composition of music, which I wish you a number of procedures including Ping
    Category: SCM Upload User:hsg5410 Size:8K
  • [Visual C++ (VC++)] ping_tracert.rar
    Category: WinSock-NDIS Upload User:wujl2008 Size:3847K
  • [Visual C++ (VC++)] zuoye4.rar Midpoint ellipse law, drawing an oval: Center (300400), rx = 200, ry = 150, ping to (200,300) rotate counter-clockwise 45 degrees
    Category: OpenGL program Upload User:yuchen0536 Size:14K
  • [VHDL] ping.rar Verilog HDL U.S. table tennis programming to learn from each other, reference, progress table tennis programming Verilog HDL
    Category: VHDL-FPGA-Verilog Upload User:xlmphoto1 Size:1K
  • [Unix_Linux] Zlg_TCP_IP.rar Week Ligong TCP/IP protocol stack, structure, clarity, simplicity, including: APRCRCETHERNETHARDWAREINCLUDEIPPINGSOCKETTCPUDP
    Category: TCP/IP Stack Upload User:huli007x Size:1393K
  • [Visual C++ (VC++)] dynamic.rar ... of the column housing modal analysis, solving of the structure before the 8-order natural frequencies and corresponding modal type. Ping framework, profiles are shown in figure 1, Figure 2. Scantlings see Table 1, Table 2. Its materials for concrete, ...
    Category: Document Upload User:lzzyjx Size:216K
  • [VHDL] EDA.rar There is a FIR filter design report there are specific code adder multiplier, etc., etc., see Cheng-Ping initiated
    Category: VHDL-FPGA-Verilog Upload User:hongsff Size:185K