切换至中文 Over 1 million code package, 10 million code file free download
  • [Visual C++ (VC++)] bitIO.rar ... , we can only make use of byte to read the contents of the documents, but we can put the contents of byte-bit computing to carry out partition, so that can be a bit to operate. Proceedings these functions were the perfect package, direct call to OK ..
    Category: File Operate Upload User:sdjinding Size:2K
  • [Java/JSP] CSVproc.zip csv operate class
    Category: File Operate Upload User:jerry77321 Size:9K
  • [Visual C++ (VC++)] Graphic.rar CArchive Class used to operate on the document. On the VC will be more familiar with the operation.
    Category: File Operate Upload User:aoqun8705 Size:87K
  • [PDF] IC.rar Non-contact IC card of digital design, how to run the card issuing device, how to operate the application
    Category: Windows Develop Upload User:mayisishi Size:48K
  • [Visual C++ (VC++)] readtxt.rar Notepad to read and write documents, TXT can directly read the contents into the system to operate within the procedures and the results written back to the new TXT file.
    Category: File Operate Upload User:joyday Size:74K
  • [Windows_Unix] Teaching.meshes.subdivision.and.multiresolution.t ... gap between raw triangle soup data and high-quality polygon meshes has driven the research on ecient data structures and algorithms that directly operate on polygonal meshes rather than on a (most often not feasible) intermediate CAD representation.
    Category: Development Research Upload User:laqi518 Size:2861K
  • [C/C++] OperatorXML.rar Easy to operate XML file.
    Category: File Operate Upload User:anywayyuan Size:59K
  • [Delphi] xmouse.zip ... to control your computer. The mouse pointer lets you select objects on the screen and operate on them. What and how you operate with the mouse is pretty simple: there s an arrow on the screen that moves when you move the mouse- ...
    Category: Delphi VCL Upload User:bhcyhxy Size:13K
  • [VHDL] ebook_Programming_Verilog_VHDL_Golden_Reference_G ... code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology ...
    Category: VHDL-FPGA-Verilog Upload User:zm130024 Size:280K
  • [C++ Builder] fseekl_binary_fwrite_fread_for_struct_array.rar Operate in binary file
    Category: Windows Develop Upload User:dingtai Size:1K