切换至中文 Over 1 million code package, 10 million code file free download
  • [Visual Basic (VB)] LanTalk_sources.zip ... computation for solving this problem. However, this comes with an expensive price, more coding, data synchronization and mess in coding logic. Additionally, I also doubt that these technologies are able to really move data across internet efficiently.
    Category: WinSock-NDIS Upload User:szqys2008 Size:489K
  • [VHDL] Alu1232.rar An 8-bit ALU with 16 operations: logic, arithmetic, shifts.
    Category: Com Port Upload User:hfdldn Size:1K
  • [MultiPlatform] Logic_Knowledge_Representation_and_Bayesian_Decis brief overviewof recentwork on uncertainty in AI, and relate it to logical representations. Bayesian decision theory and logic are both normative frameworks for reasoning that emphasize different aspects of intelligent reasoning.
    Category: Other eBooks Upload User:realfong Size:59K
  • [Visual C++ (VC++)] mcwsrc21.zip ... + added bitmaps on list box + added "No heading comments" option + added "No TODO comments" option + fixed keyboard logic and tab stops 2.1 - fixed clipboard-copy bug (Thanks to Agnel Kurian mailto:agnel.kurian@gmail.com) 2009/ ...
    Category: Windows Kernel Upload User:quli8112 Size:47K
  • [VHDL] ALU.rar ALU design in Vhdl. Arithmetic Logic Unit
    Category: Project Design Upload User:mblcsmblcs Size:3K
  • [Others] pidwphd.rar PID without PHD, usefull document on PID LOGIC
    Category: Other eBooks Upload User:tqlouisa Size:305K
  • [Matlab] FuzziLogicAndNeuronNets.RAR Fuzzi Logic and NeuralNet
    Category: SCM Upload User:xfanygy Size:1793K
  • [MultiPlatform] DigitalLogicTestingANDSimulation.rar DIGITAL LOGIC AND SIMULATION BY Alexander Miczo
    Category: source in ebook Upload User:haijun198 Size:2310K
  • [VHDL] Multiplier.rar 4 bit multiplier written in behavioral VHDL, using logic gate logic. inputs are A and B (4 bit each) and output is C (8 bits).
    Category: VHDL-FPGA-Verilog Upload User:whqzjx Size:1K
  • [VHDL] mux4x1.rar mux 4x1 with 2 control inputs, written in VHDL using 3 mathods: Logic gates, if, case. the fastest model is the one implemented with the case code.
    Category: VHDL-FPGA-Verilog Upload User:huataigj Size:1K