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  • [MultiPlatform] inface.rar an interface to the control board CPLD logic circuit design process.
    Category: VHDL-FPGA-Verilog Upload User:yaoshuwu Size:5K
  • [Matlab] bysj7.rar ... bands can automatically input signal with an average slope of the size of continuous change, decoder output signals to achieve the ideal input signal approximation, in the end programmable logic devices (FPGAs) to achieve the CVSD modulation functions.
    Category: matlab Upload User:hejinxiu Size:1K
  • [Java/JSP] CWClargemallv1.5betaversionoftheamendment ... (interface) from jsp completed and the data processed by the logic and beans completed, data storage by mysql completed. Because beans are ... for the handling of the entire site all the data logic operation, the entire site load and speed will be greatly ...
    Category: Jsp/Servlet Upload User:zhling1120 Size:1063K
  • [C/C++] upsd_logic.zip UPSD3200 Series MCU CPLD logic functions C51 Development Kit code!
    Category: SCM Upload User:wchlt918 Size:10K
  • [Visual C++ (VC++)] official.Rar evaluates truth table, a few pairs of two for evaluates, combination, and, or, etc. logic, interface, it was help documentation
    Category: GUI Develop Upload User:xxtaishan Size:47K
  • [Windows_Unix] terminalCPLDlogicengineeringdocuments.Rar realization of the project document ARM system CPLD logic, external resources have address decoding logic function
    Category: VHDL-FPGA-Verilog Upload User:xindakeji Size:116K
  • [Java/JSP] emergingwebsitedesignmethods.Rar website design method used to build MVC model, the method of achieving independence and the logic of data protection
    Category: Java eBooks Upload User:zbzhgmyxgs Size:10K
  • [Java/JSP] MVCdesignpatternsuse website design method used to build MVC model, the method of achieving independence and the logic of data protection
    Category: Other eBooks Upload User:xingdu Size:6K
  • [Visual C++ (VC++)] New_timer.rar achieve timer algorithm logic, it should not take regular drives TimerLogic achieved a simulated clock, the clock on the floor (similar hands of) 256 is a calibration of the dishes, the following four (similar minute hand of a clock) is a scale of 64 ...
    Category: SCM Upload User:tjtianjin Size:40K
  • [Java/JSP] JBuilder7Weblogic7.zip core platform 2.0 system components using J2EE technology, and adopt a framework for the use of system design, the entire system will be business logic tier system and the framework of the formation of organic layer.
    Category: Java eBooks Upload User:huakai Size:2080K