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  • [Visual C++ (VC++)] ALTERA_PCI.rar Q1 What is PCI? What are the typical applications of a PCI bus? Q2 Who governs the PCI Specification? Q3 What level of participation does Altera have in developing PCI standards? Q4 What does the designer need to know about PCI to design with our IP ...
    Category: SCM Upload User:zheng2ke Size:9K
  • [Visual C++ (VC++)] VectoMathfor3DComputerGraphics.rar ... algebra and matrix algebra from the viewpoint of computer graphics. It covers most vector and matrix topics needed for college-level computer graphics text books. Most graphics texts cover these subjects in an appendix, but it is often too short. This ...
    Category: C++ eBooks Upload User:henannaite Size:843K
  • [Visual C++ (VC++)] DriverTutorial.rar Writing drivers to perform kernel-level SSDT hooking
    Category: Hook api Upload User:amu4000 Size:1183K
  • [Java/JSP] Hello.zip which is useful to java programmer who is in novice level
    Category: Java Develop Upload User:lipengyong Size:17K
  • [VHDL] vhdl-tutorial.rar ... for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. It is intended, among other things, as a modeling language for specification and simulation. We can also ...
    Category: VHDL-FPGA-Verilog Upload User:rywx88 Size:306K
  • [Java/JSP] j2megupiao.rar ... and MIDP (Mobile Information Device Profile) APIs. As we build the application, we ll cover the following topics: · MIDlet basics · MIDP high-level user interface design · MIDP low-level user interface design · Record management system (RMS) · J2ME ...
    Category: Java eBooks Upload User:shgt256 Size:271K
  • [Others] 7levelinverterwithfilter.zip Output Filter Design for Noise Reduction of Induction Motor Driving System using H-Bridge 7-Level Inverters
    Category: SCM Upload User:tina198658 Size:22K
  • [VHDL] SystemVerilogImplicitPorts.rar ... language[3] includes two new features designed to remove much of the tedium and verbosity related to building top-level ASIC and FPGA designs from instantiated sub-blocks. These enhancements permit one of two forms of implicit port connections
    Category: VHDL-FPGA-Verilog Upload User:chuanpingl Size:62K
  • [VHDL] Fuzzy_Logic_Based_Call_Admission.rar Capacity of CDMA system depends on an interference level in the system. There are therefore RRM (Radio Resources Management) functions, which are responsible for supplying optimum coverage, ensuring efficient use of physical resources and providing ...
    Category: Other eBooks Upload User:songliuhe Size:389K
  • [Matlab] GLCM_Featuresanalysis.rar GRAY LEVEL grey level co-occurrence matrix
    Category: Windows CE Upload User:cndalang Size:62K