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  • [Unix_Linux] BSDcode.rar An implementation of the TCP/IP protocol suite for the LINUX operating system. INET is implemented using the BSD Socket interface as the means of communication with the user level.
    Category: Linux-Unix program Upload User:jiama1688 Size:157K
  • [PDF] CompilerOptimizations.rar ... to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
    Category: VHDL-FPGA-Verilog Upload User:topliulei Size:51K
  • [Java/JSP] almi.gz ALMI: Application-level Multicast Infrastructure Sherlia Shi (sherlia@arl.wustl.edu) Department of Computer Science, Washington University in St. Louis USA Please report bugs and suggestions to
    Category: Windows Develop Upload User:zhuhaiwl Size:58K
  • [C/C++] slaa134.zip ... signal, independent and asynchronous to the CPU. CPU activity and power consumption are kept to an absolute minimum level. The Timer_A3 decoder implementation also allows other tasks to occur simultaneously if required. The solutions provided are written ...
    Category: Windows Develop Upload User:hangangyx Size:9K
  • [Matlab] WZFaceDetector.rar FaceDetector is a demo for an efficient face candidates selector proposed for face detection tasks in still gray-level images
    Category: Special Effects Upload User:he75757 Size:698K
  • [PHP] 03.Skrip_dasar_PHP.zip simple php- level 0
    Category: WEB(ASP,PHP,...) Upload User:tang1250 Size:37K
  • [Matlab] binaryops.zip segmentate gray level image into binary level
    Category: Windows Develop Upload User:sdy863999 Size:6K
  • [VHDL] baughWooleyMultiplier.rar gate level implementation of 8*8 Signed baugh wooley multiplier!
    Category: Windows Develop Upload User:cxsuzhou Size:1K
  • [Visual C++ (VC++)] felt-3.06-devel.src.tar.gz ... of finite element software, the interface can also be, yes, you can try. FElt is a free system for introductory level finite element analysis. It is primarily intended as a teaching tool for introductory type courses in finite elements- probably in the ...
    Category: Algorithm Upload User:starsales Size:982K
  • [C/C++] IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE IEEE Std 1364.1-2002 IEEE Std. 1364.1- 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
    Category: VHDL-FPGA-Verilog Upload User:jianxn Size:372K