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  • [C#(.net)] frequency.rar In C sharp programming Fast Fourier Transform frequency components filtered frequency direction filter
    Category: Wavelet Upload User:hlqd188 Size:102K
  • [Matlab] DRA.zip In the analysis mode, the program calculates the resonant frequency and the unloaded Q-factor, and it estimates ... resonator dimensions that satisfy the input specifications (resonant frequency and mode, minimum bandwidth, dielectric constant, aspect ratios ...
    Category: Crypt_Decrypt algrithms Upload User:pnfjcn Size:221K
  • [Delphi] SignalDisplay.zip Displays the frequency signal of a wav file
    Category: Multimedia Develop Upload User:cnledlamps Size:321K
  • [Matlab] 5.rar routine to take the Fourier transform of a signal and plot both the time and frequency domain representations
    Category: Mathimatics-Numerical algorithms Upload User:wenhang898 Size:1K
  • [VHDL] HW3_P1.zip ... Your circuit should have an 8 position DIP Switch for setting a number “N” and a free running clock input that has a frequency is of 2.55 Mhz . The “START” signal is an asynchronous input signal which will initiate the generator such that when the start ...
    Category: VHDL-FPGA-Verilog Upload User:aseley Size:176K
  • [Matlab] CFO.zip carrier frequency offset method in WLAN - in document
    Category: Communication-Mobile Upload User:abkfld Size:2425K
  • [VHDL] wtut_ver.zip ... default, the DLL_FREQUENCY_MODE attribute is set to Low and the frequency of the clock signal at the CLKIN input must be in the Low (DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF) frequency range (MHz). See The Programmable Logic Data Book for the ...
    Category: VHDL-FPGA-Verilog Upload User:tongtsad Size:25K
  • [VHDL] wtut_vhd.zip When the DLL_FREQUENCY_MODE attribute is set to High, the frequency of the clock signal at the CLKIN input must be in the High (DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF) frequency range (MHz). See The Programmable Logic Data Book for the ...
    Category: VHDL-FPGA-Verilog Upload User:sanyouds Size:35K
  • [VHDL] rs2322.rar ... outputs is 50-50 unless CLKDV_DIVIDE is a non-integer and the DLL_FREQUENCY_MODE is High (see “CLKDV_DIVIDE,” in the Constraints Guide for details). The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute.
    Category: VHDL-FPGA-Verilog Upload User:rongda_110 Size:1579K
  • [Matlab] DigitalImageProcessingMatlabAlgorithms.rar ... Image processing algorithm implementation in Matlabs. Following are the Matlab Codes attached: Butterworth Filter in Frequency Domain Gaussian Filter in Frequency Domain Homomorphic Filter Laplacian Transform Histogram Equalization Function
    Category: Other systems Upload User:yintedz Size:4K