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  • [Others] add_3p.rar 3-stage pipeline, with 4 components of 22 full adder realize the VHDL language, applicable to altera Series FPGA
    Category: VHDL-FPGA-Verilog Upload User:gt3658 Size:2K
  • [Others] add_ff8.rar Realize the use of triggers, and 8-bit half adder of the VHDL language, applicable to altera Series FPGA
    Category: VHDL-FPGA-Verilog Upload User:yoga01 Size:1K
  • [Others] add_ff8cin.rar Flip-flop to achieve, eight full adder realize the VHDL language, applicable to altera series FPGA
    Category: VHDL-FPGA-Verilog Upload User:wilidz Size:1K
  • [Others] HIGHSPEEDDIGITALDOWNFREQUENCYTRANSFORMbasedonnewty Introduce a new type of FPGA-based high-speed digital down conversion method which realize the full advantage of digital down conversion of the optimization algorithm, as well as the field of FPGA as a result of new technology to remove data rate is too ...
    Category: VHDL-FPGA-Verilog Upload User:mt81888 Size:608K
  • [Others] vga_lcd.rar This is a VGA Nois nuclear development is the use of IP CORES in the FPGA used in the development of more
    Category: VHDL-FPGA-Verilog Upload User:necled Size:591K
  • [Others] i2c.tar.gz Verilog language I2C bus, a complete simulation. Suitable for FPGA to do the development.
    Category: VHDL-FPGA-Verilog Upload User:xwjun007 Size:686K
  • [Others] ip.rar USART the Verilog code. rar, including many of the FPGA ip source, can be applied directly uart_vhdl.zipsl811usb contains the source code. rarmc8051_design.zipmcpu_1 [1] .05. zipminicpu.zipmmc_lark_original.zip
    Category: VHDL-FPGA-Verilog Upload User:jhon1234 Size:5265K
  • [Others] dds.rar FPGA realization of direct digital signal source. A phase accumulator design
    Category: VHDL-FPGA-Verilog Upload User:bbedward Size:5K
  • [Others] vhdl_CIC.zip FPGA introductory information comes from a division of Taiwan s internal training materials
    Category: VHDL-FPGA-Verilog Upload User:deweite888 Size:2946K
  • [Others] designconstraint.rar Senior FPGA Design Method- bound (xilinx corporate training information)
    Category: VHDL-FPGA-Verilog Upload User:biz_yang Size:367K