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Matlab]
VHDLDelay.rar
Development environment is the FPGA development tools, is described in VHDL delay procedures, the article also have procedures
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Matlab]
geleicounter.rar
Development environment is the FPGA development tools, Gray code counter VHDL procedures
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Others]
sbq.rar
07 National Undergraduate Electronic Design Contest winning entries C title FPGA core of the source (EP1C6Q)
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Others]
abc.rar
: In the FPGA to achieve the high-frequency narrow-band digital signal of the down-conversion and sampling rate conversion, due to completely avoid the need for a large number of logic resources and digital multiplier oscillator, greatly simplifying its ...
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Others]
234.rar
... and principle. Finally, with the adoption of Simulink for digital down-conversion performance of the simulation. In the simulation based on the use of Insight s FPGA development system is measured using the test circuit of the digital down-conversion of
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Others]
up_261128143F5F01A9.rar
... algorithms. The algorithm can be adapted to low signal to noise ratio, broadband rates offset the scope of bad communications environment and unexpected modes of communication, and the algorithm complexity low. The algorithm has been realized in the FPGA.
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Others]
vietro-pro.rar
Carefully collected vietro pro Xilinx s FPGA-Series datasheet and usreguide, these two technical documentation is that we use the series FPGA chip main reference manual!