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TEXT]
scu_all_fpga.rar
large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
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Windows_Unix]
VgaChinese.rar
on display in Chinese characters, achieving the FPGA, using Verilog HDL design, However, the use of direct completely
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Windows_Unix]
seg_led_rtl.rar
FPGA use of digital control in the digital tube dynamic display figures that use, direct module as other sub-module, called directly
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[
Others]
System09.rar
BurchED B5- X300 Spartan2e using XC2S300e Top level device file for 6809 compatible syste m on a chip Designed with Xilinx XC2S300e Sparta n 2 FPGA. Implemented With BurchED B5- X300 FPGA board, B5-SRAM module, B5-CF module and B5- FPGA-CPU-IO module