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keyword: fpga

  • [VHDL] fifo.rar The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
    Category: VHDL-FPGA-Verilog Upload User：jzy028 Size：161K
  • [VHDL] and_2.rar The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve an AND gate.
    Category: VHDL-FPGA-Verilog Upload User：chinalszl Size：167K
  • [VHDL] ram.rar The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.
    Category: VHDL-FPGA-Verilog Upload User：szlbled Size：194K
  • [VHDL] rom.rar The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.
    Category: VHDL-FPGA-Verilog Upload User：lyx1230vip Size：175K
  • [VHDL] signal_output.rar The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
    Category: VHDL-FPGA-Verilog Upload User：max_guan Size：1133K
  • [VHDL] shumaguan.rar fpga under the seven-segment digital tube experiment reports that the University
    Category: VHDL-FPGA-Verilog Upload User：shjinyudz Size：220K
  • [VHDL] DDS.rar This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.
    Category: VHDL-FPGA-Verilog Upload User：lee2797 Size：473K
  • [VHDL] LC_txmit.rar FPGA UART transmit and so on
    Category: VHDL-FPGA-Verilog Upload User：plf000 Size：1K
  • [VHDL] FPGACOM.rar FPGA programming serial communications, the entire source code. Including the simulation program.
    Category: VHDL-FPGA-Verilog Upload User：yuandalvye Size：1K
  • [VHDL] FPGAPROGRAMCHAPTER6.rar FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.
    Category: VHDL-FPGA-Verilog Upload User：szlh168 Size：21K