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  • [MultiPlatform] Reliability.rar A stochastic-flow network consists of a set of nodes, including source nodes which supply various resources and sink nodes at which resource demands take place, and a collection of arcs whose capacities have multiple operational states.
    Category: WinSock-NDIS Upload User:jieneng Size:112K
  • [Visual C++ (VC++)] tracker.zip ... flow algorithm was used Accurate optical flow computation under non-uniform brightness variations article may Algorithm-optical flow in the calculation algorithm, Accurate use of optical flow computation under non- uniform brightness variations article ...
    Category: ActiveX-DCOM-ATL Upload User:hbzhengda Size:1136K
  • [Java/JSP] Thinking_in_Java_3rd_edition.zip ... Revision 4.0 Preface Introduction 1: Introduction to Objects 2: Everything is an Object 3: Controlling Program Flow 4: Initialization & Cleanup 5: Hiding the Implementation 6: Reusing Classes 7: Polymorphism 8: Interfaces & ...
    Category: Java Develop Upload User:shyy7758 Size:1220K
  • [Java/JSP] NL-flow.rar Newton- Raphson load flow calculation program
    Category: Other Industry Upload User:rxbkf120 Size:2K
  • [WINDOWS] SoC.rar SoC Design Flow and Tools
    Category: E-Books Upload User:baoling Size:491K
  • [Others] ASIC_Design_Flow_Tutorial.rar ASIC Design Flow Tutorial, explain the ASIC design flow, ultra-detailed documentation.
    Category: SCM Upload User:btjhwmj Size:3909K
  • [PDF] FPGA_Flow.rar fpga design flow from Xilinx
    Category: VHDL-FPGA-Verilog Upload User:lsl162 Size:151K
  • [Unix_Linux] dsr-uu-0.2.rar ... ns-2 network simulator. DSR-UU implements most of the basic DSR features specified in the DSR draft (version 10). One big exception is flow extensions. DSR-UU does NOT use ARP, so do not be surprised if you do not see ARP traffic. DSR-UU instead ...
    Category: Linux Network Upload User:elite_cas Size:240K
  • [Others] DSP_WITH_FPGA.rar The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP ... how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on ...
    Category: DSP program Upload User:slmbla Size:9703K
  • [VHDL] pcie_vera_tb_latest.tar.gz FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number ...
    Category: VHDL-FPGA-Verilog Upload User:sxdewei Size:166K