切换至中文 Over 1 million code package, 10 million code file free download
total: 9768
code resource search result

keyword: features

  • [Delphi] pasview.zip Pascal Viewer This is a simple Application to convert Pascal Source Texts to Rich Text Format with Syntax Highlighting. Main features: Reading from file or copying from Clipboard, saving to RTF or printing. Different font names, size, color, ...
    Category: Windows Develop Upload User：wcfengji Size：11K
  • [Matlab] EdgeFeatureExtraction.rar Extract Edge Features using these operators
    Category: matlab Upload User：gl09216 Size：3K
  • [C/C++] SEA_OF_C.zip This gives a breif intoduction to c and some key features in c
    Category: Other systems Upload User：itsemi Size：5K
  • [C#(.net)] wenben.rar Can be achieved with a text editor that comes with windows xp notebook features similar！
    Category: E-Books Upload User：wishlxc Size：11K
  • [C/C++] c30_modules.zip implemented as a C library. Only the features used by the application are brought into the final image. The minimal footprint of ThreadX is under 2KB on Microcontrollers.
    Category: Windows Develop Upload User：ougemaled Size：7152K
  • [Others] OperatingSystemUbuntu.rar A complete research carried on Ubuntu operating system. includes all its features, how to install, its kernal, shell and many more details.
    Category: Development Research Upload User：hsj248 Size：3928K
  • [Windows_Unix] tut_simulation_verilog.rar This tutorial introduces the basic features of the QuartusII Simulator.
    Category: VHDL-FPGA-Verilog Upload User：szshuawei Size：294K
  • [MultiPlatform] eBook.McGraw.Hill.Osborne.Oracle.Database.10g.SQL This comprehensive text explains how to use the latest Oracle Database 10g features, how to perform complex calculations using analytic functions, and how to use large objects to store character and binary data.
    Category: Windows Develop Upload User：jzhydz Size：832K
  • [VHDL] SystemVerilogImplicitPorts.rar The Accellera SystemVerilog language[3] includes two new features designed to remove much of the tedium and verbosity related to building top-level ASIC and FPGA designs from instantiated sub-blocks. These enhancements permit one of two forms of ...
    Category: VHDL-FPGA-Verilog Upload User：chuanpingl Size：62K
  • [Unix_Linux] linuxmemory.rar linux memory managment with all features
    Category: File Formats Upload User：sdhygg2008 Size：13K