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[
VHDL]
crc_verilog.rar
Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
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MultiPlatform]
H.264.rar
This book, introducing digital video and video encoding based on the basic principles, discusses the characteristics of H264, encoder principle, the principle of the decoder and codec realization of the program.
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Matlab]
GSM-TCH-FS.rar
GSM TCH/FS channel coding simulation Simulation of communication systems, including internal and external encoder, interleaving rearrangement, and additive/sudden or mixed channel interference, de-interlacing anti-rearrangement, and internal and external ...
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VHDL]
qep.rar
A QEP circuit Verilog code. Input signal is the optical encoder of the A phase and B and believe that a deal with the clock, the output is the count signal and direction signal.
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[
Visual C++ (VC++)]
clock.rar
Answer the number is controlled by the main circuit and the expansion of circuit components. Priority encoder circuit, latch, decoder circuit will be teams of the input signal in the display output with control circuitry and the host switch alarm ...
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Visual C++ (VC++)]
complier.rar
FPGA realization of the conversion process cpu binary encoder, in order to realize and test the machine language to help