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keyword: edge

  • [VHDL] counter_advanced.rar A counter that starts from 0 and increments mod 16 on each rising edge of the clock
    Category: VHDL-FPGA-Verilog Upload User：shgomarket Size：1K
  • [C/C++] GRAPH.rar Given the edge set Draws the graph.......
    Category: Graph Drawing Upload User：tangyi0510 Size：1K
  • [Matlab] edge.rar Image through edge detection to find the center coordinates of the dots
    Category: Special Effects Upload User：dztykt Size：582K
  • [Visual C++ (VC++)] sobel.rar Sobel Edge Detection of an Image. Edge Detection using Sobel MAsk
    Category: Graph program Upload User：jinsuping Size：4K
  • [Visual C++ (VC++)] SobelEdgeDetection.rar Sobel Edge Detection of an Image. Edge Detection using Sobel MAsk
    Category: Graph program Upload User：ctjdss Size：4K
  • [Visual C++ (VC++)] edge.rar OPENCV based on image edge detection, (VC++) Using canny edge algorithm to find the image and re-exported in the symbol.
    Category: Special Effects Upload User：zlf790605 Size：104K
  • [MultiPlatform] Canny.rar Edge detector of Canny.
    Category: matlab Upload User：szsspd Size：2K
  • [VHDL] EX.rar ... Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it ...
    Category: VHDL-FPGA-Verilog Upload User：cnzheguang Size：5K
  • [VHDL] 1_LAB.rar ... Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it ...
    Category: VHDL-FPGA-Verilog Upload User：szcomorg Size：5976K
  • [Matlab] Edge-Detection-Color.rar Mainly on the color image edge extraction of the source code. Which contains the picture to be addressed, as well as all the source code, that is, M documents.
    Category: matlab Upload User：sdxlgg4493 Size：1010K