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[
VHDL]
vhdl_edge_ris.zip
rise edge detecting some signal module...
tested by Altera MaxPlusII or Quatus II
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[
VHDL]
Long_shift_gate_level.zip
... Output pins: OUT [15:0].
4.
Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge.
5.
The SHIFT signal describes the shift number. The shift range is 0 to 15.
6.
When the signal RIGHT is high, ...
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[
VHDL]
STUDENTS_SCORE.zip
... is allowed.
5. All input signals will be changed at negative edge of clock. IN_VALID is high
when INPUT [6:0] is valid. ... .timing is
non-negative.
10. All outputs are sampled at negative clock edge.
11. The clock period is 5 ns.
12. The output loading ...
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[
Matlab]
shearlet.rar
Analysis of Singularities and Edge Detection using the Shearlet Transform
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