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keyword: dds

  • [C/C++] DDS_Single.rar DDS sine wave generated source code through the debugger to normal use
    Category: SCM Upload User：schd666 Size：1K
  • [VHDL] FPGA_signal_general.rar Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are given Altera-based FPGA devices the company a three-phase sinusoidal signal generator design program, at the same time give its software programs and simulation results. The ...
    Category: VHDL-FPGA-Verilog Upload User：zjp003003 Size：100K
  • [VHDL] FPGADDS.rar FPGA-based signal generator DDS simple to achieve. DDS (direct digital synthesis) is a rapidly in recent years developed a new method of frequency synthesis. This method is simple and reliable, convenient control, and has a very high frequency resolution ...
    Category: VHDL-FPGA-Verilog Upload User：xadufang Size：10K
  • [C/C++] dds_basic.rar ac example of dds module
    Category: SCM Upload User：shhuangyj Size：2K
  • [VHDL] high_speed_tap8_DDS.rar Verilog prepared with high-speed 8-way parallel dds modules for use with high-speed da (1ghz or above) interface have any frequency sine wave, the module has been proof for the products.
    Category: VHDL-FPGA-Verilog Upload User：hmctj1 Size：5K
  • [C/C++] dp_test.rar This procedure is used VHDL language, including the parallel port communication, DDS motor, encoder signal processing and so on, to look at this area of engineering staff have a certain reference
    Category: VHDL-FPGA-Verilog Upload User：ksmsdsy Size：589K
  • [VHDL] dds_using_FPGA.rar FPGA realization of the use of DDS compiled no errors. Compiler environment QuartusII7.2, the environment integrated IP core, can improve the development efficiency.
    Category: VHDL-FPGA-Verilog Upload User：jndfzc Size：98K
  • [C/C++] Lowfrequencydigitalphasetester.rar ... and phase-shifting network of three modules, respectively, by two independent single-chip control and display functions. Using DDS technology to generate two sinusoidal signals, and by changing the data memory read start address to the realization of ...
    Category: SCM Upload User：peng0298 Size：263K
  • [VHDL] ddszh.rar FPGA DDS shuzhi xinhao
    Category: VHDL-FPGA-Verilog Upload User：xttarrk Size：321K
  • [Matlab] observationDDSoutputwaveform.rar MATLAB observation DDS output waveform：Read. Tbl hexadecimal content of the document and digital conversion as a decimal number, the output sinusoidal waveform
    Category: Other systems Upload User：jamesfzj Size：3K