cpld code resource search result, page 92, Verysource

[VHDL] eda.rar the map of cpld developed board。
Category: VHDL-FPGA-Verilog Upload User：xingmingsy Size：93K
[VHDL] vhdl-TAXI.rar ... of EDA technologies and large-scale programmable logic device CPLD/FPGA emergence of electronic systems design techniques and tools has undergone tremendous changes, through the EDA technology CPLD/FPGA programming product development, not only low-cost, ...
Category: software engineering Upload User：huiyuanjf Size：263K
[VHDL] DOC.rar To switch relays using CPLD
Category: VHDL-FPGA-Verilog Upload User：liuweicom Size：1022K
[WORD] fpgacpld.rar about FPGA CPLD
Category: source in ebook Upload User：sxxjzj Size：41K
[VHDL] PLCC84_Socket_mdy.rar PLCC84 socket package, for example, and so on cpld chip EPM7128slc84
Category: VHDL-FPGA-Verilog Upload User：bayesic Size：4K
[PDF] Motor_drive_board.rar Motor drive board, using ipm, cpld protection, current and voltage detection, signal processing encoder
Category: Driver Develop Upload User：fanhw64 Size：91K
[Visual C++ (VC++)] AD_DA.rar dsp2407+ cpld experimental version of the source of ad_da input conversion source, which leads the 16-channel and 8 channel 0.
Category: SCM Upload User：huierle Size：67K
[Others] quaddecoder_verilog_ise11.2_used_09042010.rar Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need ...
Category: VHDL-FPGA-Verilog Upload User：wmy1000 Size：69K
[Visual C++ (VC++)] E-clock.rar E-clock training cpld the original project code, sub-modules, to achieve timing, timer, led display
Category: SCM Upload User：jinyingby Size：117K
[Visual C++ (VC++)] E-clock.rar cpld project training program electronic clock, sub-modules, to achieve timing, timer, led display
Category: SCM Upload User：jantonliu Size：24K

keyword: cpld