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VHDL]
cp_uart_6.rar
Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
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[
VHDL]
example10.rar
Cpld based on the controllable pulse generator cpld based on the controllable pulse generator based on the controllable pulse generator cpld
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[
VHDL]
EPM240_SCH_and_program.rar
Schematic diagram+ EPM240 cpld procedures. Sine wave generator procedures, ADC0804 DC sampling and showed that Chinese scroll, traffic lights, keyboard, display program, counters and so on.
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C/C++]
pwmcon.rar
mega128 and CPLD key combination to change the PWM duty cycle control at the same time expand the board CPLD button control I/O output control voltage
Category:
SCM Upload User:
sunmu518 Size:
25K
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[
VHDL]
get_6675_temp_2.rar
... , Quartus II 6.0 transfer is approved, the development board cpld successfully tested above.
The MAX6675 performs cold-junction compensation
... C, and exhibits thermocouple
accuracy of 8LSBs for temperatures ranging from
0°C to+700°C.
controller is cpld
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WORD]
325.zip
CPLD download line information system to do, I have produced based on this success, can be downloaded and there is a very good version of the FPGA system
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Others]
PID.rar
In this paper, the use of hardware description language written in vhdl hardware PID algorithm in FPGA/CPLD
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