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dualportRAM.zip
dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
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vhdl_clock.zip
VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in ...
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vhdl_i2c.zip
... IIC EEPROM Access Interface Development Board experimental pressed a button keyboard CPLD code will go into the data switch E EPROM a ... , pressed another button, just write the data back to reading CPLD, and the digital pipe show. To help readers master the ...
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modianshiyan_1.rar
... understanding of the development of the whole process of CPLD. ◆ learn to use software simulation and hardware realization of digital logic circuits to verify functionality and analysis. ◆ CPLD development through realization of the reverse function of ...
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SCM Upload User：
hhyzlrm Size：
25K
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taxi_counter.rar
a taxi prepared by the accounting device, starting six yuan or 2 km, then every half kilometer or 0.8 yuan, stopping to wait for every 2.5 minutes or 0.8 yuan. Through simulation, but not download to test CPLD
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cpldand8051.rar
cpld and SCM 8051 communication methods and the design and cpld corresponding port MCU
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SCM Upload User：
lbl0218 Size：
8K
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