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Windows_Unix]
app.rar
FPGA应用，Altera的FPGA开发板原理图汇集，FPGA最小系统，rs232串口转换，VGA显示-FPGA applications, Altera s FPGA development board schematic pooling, FPGA minimum system, rs232 serial converter, VGA display etc.
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VHDL]
Binary_to_BCD_Converter.rar
General Binary-to-BCD Converter
The linked code is a general binary-to-BCD Verilog module, and I have personally tested the code.
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Matlab]
Soft_demapping_QPSK.zip
soft Demapping QPSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter : needs I and Q components of QPSK symbols at the input
Category:
matlab Upload User：
liquan0105 Size：
1K
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Matlab]
Good_ver_Soft_demapping_QPSK.zip
good version of soft Demapping QPSK : LLR computation using Euclidian distance approache, Parallel-to-Serial converter, needs I and Q componets of QPSK symbols at the input
Category:
matlab Upload User：
szyuanwd Size：
1K
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Matlab]
Soft_demapping_8PSK.zip
soft Demapping 8PSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, needs I and Q componets of 8PSK symbols at the input
Category:
matlab Upload User：
newvector Size：
1K
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Matlab]
demapping_soft_QPSK_good_version.zip
corrected version of Demapping QPSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, needs I and Q componets of QPSK symbols at the input
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Matlab]
Hard_decision_demapping_8PSK.zip
Demapping 8PSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, Hard decision, needs I and Q componets of 8PSK symbols at the input
Category:
matlab Upload User：
cdjbfh Size：
1K
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