clock code resource search result, page 72, Verysource

[Visual C++ (VC++)] clock.rar Realize the use of the memory clock procedures canvas. At the same time, snow has fallen on the pointer on the clock. Using multi-threaded graphics production.
Category: GDI-Bitmap Upload User：cinwell Size：50K
[VHDL] clock.rar designed Clock(minutes and second) by Verilog HDL
Category: VHDL-FPGA-Verilog Upload User：orville_se Size：244K
[Visual C++ (VC++)] Clock.rar A simple digital clock procedures, in which category the date derived from MFC CStatic base class.
Category: Other windows programs Upload User：lizhi_528 Size：120K
[C++ Builder] clock.rar clock
Category: 2D Graphic Upload User：sucwang Size：348K
[Unix_Linux] common.zip u-boot loader common files, like cpu, clock, environment...etc...
Category: Linux Network Upload User：mgl_018 Size：858K
[Others] clock-51.rar 51 Single-chip electronic bell procedures, with the whole point of time can be set-up times, in order to point out to preserve function. Singlechip clock with 12M, have been tested very accurately.
Category: ARM-PowerPC-ColdFire-MIPS Upload User：gogogff Size：39K
[Matlab] calculatePseudoranges-trial.zip ... finds relative pseudoranges for all satellites listed in CHANNELLIST at the specified millisecond of the processed signal. The pseudoranges contain unknown receiver clock offset. It can be found by the least squares position search procedure.
Category: GPS develop Upload User：htl007 Size：1K
[Visual C++ (VC++)] clock.rar Under the blue screen shows a moving clock, it did not take the ring for about one second, with the system clock synchronization, you can set the time
Category: Windows Develop Upload User：wodeyou520 Size：37K
[VHDL] work.zip Clock for any purpose of use by any design
Category: Project Design Upload User：bauuuwl Size：451K
[VHDL] simple_spi.tar.gz ... programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface. Very simple, very small.
Category: VHDL-FPGA-Verilog Upload User：dostar Size：561K

keyword: clock