circuit code resource search result, page 95, Verysource

[VHDL] EDAandVHDL.rar EDA technology and VHDL practical circuit design stepper motors and DC motor control, VGA display controller design, storage oscilloscope design, universal asynchronous receiver design, frequency, phase meter design, DDS design,
Category: VHDL-FPGA-Verilog Upload User：cyc8810 Size：1535K
[Visual Basic (VB)] xsp.rar This is a PROTEL map is to show the circuit schematic diagram disk, we can refer to, learning how to use the schematic diagram
Category: Embeded-SCM Develop Upload User：yayayi Size：2K
[Others] DIGTIAL_CLOCK00.rar The design of multi-functional digital clock to analog circuits for the theoretical basis for the 555 processor chip as the main pieces of functionality, coupled with the external circuit, constitute a simple and practical multi-function digital clock.
Category: Other eBooks Upload User：jjh5213 Size：63K
[Others] clockcircuit(designedbyat89c51).rar clock circuit based on AT89C51
Category: SCM Upload User：lslccc Size：399K
[C/C++] protel.rar What has, is to stew. Electronic professional good information. Electronic circuit schematics download electronic data to study the electronic production of electronic single-chip technology
Category: SCM Upload User：szylda Size：4344K
[Visual Basic (VB)] 200682219153.rar Receiving unit, we have adopted the principle and the principle of like FM radio. Figure 3 for the receiver circuit to a dedicated IC1 TDA7021T FM receiver module as the core, after demodulation of the audio signal after the output from the feet, to make ...
Category: Windows Develop Upload User：aqingfeng Size：47K
[VHDL] EDA.rar Digital circuit EDA entry-VHDL instance Set Beijing University of Posts and Telecommunications Press
Category: Other eBooks Upload User：btfamen Size：2910K
[DOS] swfdecchs.zip Static RAM is a tube composed of MOS flip-flop circuit, each flip-flop can store one message. Long as it does not ... , the static stability in the work RAM, do not refresh plus the new circuit and easy to use. But generally each SRAM trigger is composed of ...
Category: VHDL-FPGA-Verilog Upload User：iviled Size：3153K
[VHDL] final_1.rar 1. For the key input, please join the voice output circuit, representing the keys sw1 feedback of the audio message. Every time when sw1 button depressed, they sent 0.1 seconds of sound 1KHz.
Category: VHDL-FPGA-Verilog Upload User：lshk_yk Size：574K
[C/C++] power.rar Electronic Energy Meter Design related, reference circuit good article
Category: Software Engineering eBooks Upload User：qzhcgyjg Size：267K

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