切换至中文 Over 1 million code package, 10 million code file free download
  • [Visual Basic (VB)] PDUEncoder_src.zip ... and gives a convience way to get PDU Encoder by simply set some properties. This program is only a demo, so the code is not very well written. Maybe some bugs are hidden, and some cashed may happen.You can use this code as the base of your project.
    Category: SMS Upload User:koyaalight Size:3K
  • [Visual C++ (VC++)] tuxiangchuliruanjiian.rar ... It inclu des load/save, display, histogram, and undo/redo and over 100 predefined filters. It i s a mature and easy-to-use image library that ev eryone from novices to professionals can use an d enjoy. one expert wrote, I finally found. and share with you
    Category: Special Effects Upload User:tuxiaojuan Size:1216K
  • [Delphi] dsreportdemo.zip Compact report generator with many nice features. Uses dsPrinter so it can do much more than just reports.
    Category: Printing program Upload User:shengmaosh Size:2447K
  • [Matlab] xml.zip With this tool you can convert strings and files containing XML data to MATLAB struct arrays. Either as one array of ... ter 2002, Mitthö gskolan, SWEDEN This program is free software you can redistribute it and/or modify it under the terms of the GNU ...
    Category: 2D Graphic Upload User:gyrfy08 Size:28K
  • [Matlab] lvm_import09.zip ... , lvm_import.m, reads LVM files and imports the data into the MATLAB workspace.LVM is an ascii text file format, and the data can be imported into MATLAB using the built-in import.m function. However, import.m has some limitations: it cannot handle multi- ...
    Category: Button control Upload User:mhncmhnc Size:3K
  • [Others] CLOCK_co-design_of_C_and_Verilog.rar A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
    Category: Other systems Upload User:yisteven Size:37K
  • [Others] Find_medium_value_co-design_of_C_and_Verilog.rar A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
    Category: Other systems Upload User:liaoyt_253 Size:11K
  • [C/C++] CANRkeyok2.rar CAN-bus master and slave connections, to ensure that their communications
    Category: Other Embeded program Upload User:oliverlia Size:82K
  • [Others] Traffic_sign_co-design_of_C_and_Verilog.rar This is an extension of sign example. You can design your own traffic sign by using Verilog. And the result from Verilog can be seen by the attached C file.
    Category: Other systems Upload User:hr2818 Size:254K
  • [Asm] snake.rar This is the snake game... It s better to set the "step delay" to "0" before running, it requires fast processing. You can control the snake using arrow keys on your keyboard. All other keys will stop the snake. Press ESC to exit.
    Category: assembly language Upload User:lakiail Size:2K