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  • [VHDL] alu.rar This arithmetic logic unit accepts 8-bit inputs, but it can easily be modded to higher bits. It supports the addition, subtraction, set if less than, AND, and OR operations. The operation to perform is determined by the 3-bit address bus.
    Category: VHDL-FPGA-Verilog Upload User:hnygfy Size:1K
  • [Matlab] script_ber_msk_awgn.zip The file computes the bit error rate for MSK
    Category: matlab Upload User:olpnick Size:2K
  • [C/C++] Improved-parallel-weighted-bit-flipping.rar LDPC codes in parallel weighted bit flipping algorithm can achieve good decoding performance is a very good article
    Category: WinSock-NDIS Upload User:wldqxszx Size:187K
  • [PDF] intel_32bit_manual_vol_1.rar This is the volume 1 of intel 32/64 bit processor.
    Category: Windows Develop Upload User:awei524 Size:2530K
  • [PDF] intel_32bit_manual_vol_3.rar This is the volume 3 of intel 32/64 bit processor.
    Category: Embeded-SCM Develop Upload User:hsdsh2008 Size:4138K
  • [VHDL] AES_128.rar 128 bit Advanced Encryption Standard
    Category: Crypt_Decrypt algrithms Upload User:xq1107 Size:49K
  • [C++ Builder] OUXCOMM.ZIP comm rs232 TXComm and TXModem are 32-bit native VCL components designed for Delphi 4-? and C++ Builder 4-?. These two components encapsulates main characteristics of communication devices and their behavior.
    Category: Delphi VCL Upload User:shousj0061 Size:212K
  • [C/C++] KKLcd.zip code for LCD interfacing with controller starting steps to LCD initialization in 4 bit mode
    Category: Other Embeded program Upload User:hedepei Size:1K
  • [VHDL] TIC_TAC_game_gate_level.zip ... : TT (Filename: TT.v) 2. Input pins: IN_AtoI [8:0] 3. Output pins: OUT [1:0] 4. All of the input are 1-bit numbers. 5. You can only use the following gates in Table I, and it its neede to include ALL the delay information (Tplh, Tphl) in your design. ...
    Category: Project Design Upload User:gracehts Size:258K
  • [VHDL] convolution_calculator_4_bits.zip convolution is important and is widely used in digital signal processing.For example, in LTI system. Input two sequences of 8-bit 2 s complement signed numbers with length 2~8. the input values range is -128~127.
    Category: VHDL-FPGA-Verilog Upload User:daichengfu Size:5348K