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C/C++]
DMA.rar
... soon as the transfer is completed an interrupt isgenerated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data counter is stored before and after the transfer to show that all data has beentransfered. ...
Category:
SCM Upload User：
bjlll8 Size：
496K
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Others]
16bit_microprocessor.rar
This is a 16bit 8086/8088 intel style microprocessor, which has main basic function and an internal memory, 16* 256 bit size. Thank you.
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C/C++]
BIT.rar
HC12DG128A bit operating instructions apply to HC12 and HC (S) 08, taking into account the speed of
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nbdeying Size：
1K
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VHDL]
bit-catchingupFPGA.rar
This article is in the FPGA, the realization of the receiver bit synchronization circuit article introduces the realization of the methods.
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VHDL]
8b_10b.rar
... active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/ ... clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes ...
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VHDL]
ci8534tm1.rar
Analog signals are represented by 64 bit buses. They are converted
to real and from real representation using PLI functions
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Others]
1.rar
MSK English information on the Bit Error Performance Analysis of FH/MSK Systemin Different Multi-tone Noise Jamming
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Unix_Linux]
md5coll.c.gz
MD5 Collision Generator.
A few optimizations to make the solving method a bit more deterministic
Category:
Exploit Upload User：
lhlart Size：
7K
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Visual C++ (VC++)]
huffman_src.zip
... in that file s1(1000), s2(200), s3(30) so the total length of file is 1000+200+30=1230 bytes, it will be encoded assigning one bit to s1 and 2 bits to s2, s3 so the encoded length will be 1*1000+2*(200+30)=1460 bits=182 bytes). In the best case the file ...
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