VHDL FPGA Verilog&page=8 code resource search result, page 1, Verysource

[VHDL] Flashcontrollerxilinx.rar ... I/O tolerance n Automated Program and Erase — Page program: 512+ 16 bytes — Block erase: 8 K+ 256 bytes n Block ... byte spare area (separately erasable, readable, and programmable) — 512 byte page+ 16 byte spare area for ECC and other system overhead ...
Category: VHDL-FPGA-Verilog Upload User：czslss Size：828K
[VHDL] Spartan3VGATest.zip This VGA test will draw a single color page and change color every one second. VGA resolution is 640x480 @25 MHZ 8 colors
Category: VHDL-FPGA-Verilog Upload User：whchangjin Size：516K