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Others]
jiekou.rar
... controlled by two-run shot eight manner. Press the start switch SW1 when the stepping motor, according to ESC key to stop working. Adopt the cycle look-up table method, using software to achieve the function of pulse cycles distributor winding rotation ...
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Delphi]
lansheng.rar
Try for implementation of the functional picture, click to start try for, try for picture automatically, try for at click stop to stop!
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VHDL]
uart8.zip
... the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
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VHDL]
UART.rar
Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data, send data back data+1
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Asm]
steppermoter1.rar
Containing Proteus simulation, including the stepper motor is, reversal, acceleration and deceleration, and stop functions.
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SCM Upload User：
dezhouqiye Size：
17K
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C/C++]
musicctrol.rar
... order to achieve short procedure to play music. 2 using LDM lattice to show the size of the voice. 3 implementation cycle of play, stop and resume playback, such as a 4 under the use of LCD display song information, and as the songs play, pause and resume ...
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SCM Upload User：
hadj518 Size：
362K
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