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[
WINDOWS]
fir_filt.rar
Implementation of FIR filter with the MAXQ Multiple-And-Accumulate unit specify module and ROM routine definition files
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[
Others]
AD_fir.rar
speech signal achievement of the AD converter FIR filtering, In TMS320VC5402 DSP development board through debugging
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VHDL]
tdmddc_v61.zip
Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
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VHDL]
myfir.rar
The use of fir filter ip-core design of filters, the data for the 16bit, rate 61.44mhz, working clock 245.76mhz
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[
Matlab]
fir_16.rar
fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
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Matlab]
firmatlab.rar
fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim