-
-
[
Visual C++ (VC++)]
DF1404B0808.rar
DDS generation process, enabling the compiler and debug waveform waveform amplitude, as well as cycle waveform
Category:
SCM Upload User：
xuhui4415 Size：
270K
-
[
C/C++]
9851.rar
51 single-chip DDS control procedures have FM function and direct input
-
[
VHDL]
07_DDSmokuai.rar
DDS module EWB Quartus2 chamber compile electronic integrated design process
-
-
[
Others]
dds_new.rar
Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
-
[
VHDL]
AM.rar
AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
-
[
Visual Basic (VB)]
clk.rar
Modern electronic system design is based on DDS technology courses use VHDL to design and produce a digital shift Signal Generator. (1) the basic requirements: a. Frequency range: 1Hz ~ 4kHz, frequency step for the 1Hz, output frequency can be preset. b. ...
-
[
VHDL]
sin125.rar
Using FPGA to achieve DDS signal generator (sine wave 125kHz)
-
[
VHDL]
Sinout.rar
dds controllable sinusoidal occurred wholly the result of use of matlab, dsp, Quartus II 6.0 software
-
[
Asm]
ex4.rar
VC33 through pc input to change the DDS frequency generator, can achieve single-frequency signal and FSK signal
切换至中文 Over 1 million code package, 10 million code file free download 
