DDS code resource search result, page 11, Verysource

[VHDL] dds.rar The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Category: VHDL-FPGA-Verilog Upload User：qdzj117 Size：186K
[VHDL] dds.rar How to make use of DDS generated FM signal FPGA specific
Category: VHDL-FPGA-Verilog Upload User：gakaeg Size：739K
[VHDL] DDS.rar DDS frequency synthesizer (using VHDL hardware description language, through the development of Altera QuartusII)
Category: VHDL-FPGA-Verilog Upload User：jilin_l Size：228K
[PPT] DDS.rar DDS digital synthesis technology on system design, that is, a number of important concepts and principles, there are the typical attributes and compare DDS chip
Category: SCM Upload User：amy_4665 Size：2251K
[C/C++] dds.rar msp430f149 ad9851 dds
Category: SCM Upload User：dgsmpost Size：20K
[VHDL] DDS.rar Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ
Category: VHDL-FPGA-Verilog Upload User：sunping666 Size：115K
[VHDL] FPGA-DDS-FM.rar DDS signal generator FM Design Principle diagram
Category: Communication Document Upload User：jtqc666 Size：68K
[PDF] DDS.rar With regard to the design of DDS with AD9852 chip to complete the relevant information of a more comprehensive
Category: Other Embeded program Upload User：ltxz37 Size：7393K
[C/C++] DDS.rar Debugging experience of DDS in PDF document, the driver code AD9850
Category: SCM Upload User：mingshimsn Size：1236K
[VHDL] DDS.rar Quartus on the DDS, can occur sine wave, square wave, triangle wave, with the top-level documents, notes in the procedure
Category: VHDL-FPGA-Verilog Upload User：wangqs Size：76K

keyword: DDS