CPLD code resource search result, page 96, Verysource

[Windows_Unix] pulsemindwhenCPLD.rar principle : pulse input, recording 30 pulse interval (total time), the LED display and digital control involves rotating lights, and LED yards. Input port must use the entire 000 74LS14 that there is no map. Digital control the use of digital control ...
Category: VHDL-FPGA-Verilog Upload User：yingda8 Size：630K
[Windows_Unix] RAMINCREASE.rar CPLD This is done using the DSP memory expansion of the source document.
Category: VHDL-FPGA-Verilog Upload User：ashurum Size：6K
[Windows_Unix] primetime.rar This is the VHDL language delay the test procedure used to determine the performance CPLD
Category: VHDL-FPGA-Verilog Upload User：tuoranled Size：51K
[MultiPlatform] CPLD--VHDL.rar VHDL basic knowledge, everything from the foundation started! We hope that the right help!
Category: VHDL-FPGA-Verilog Upload User：humenshu Size：30K
[PDF] cpld.zip.rar html test test test
Category: Windows Develop Upload User：lcyc2011 Size：364K
[C/C++] idedriver.rar ide the lower driver. A project (cpld+ dsp) part.
Category: DSP program Upload User：llxups123 Size：57K
[Others] FPGACPLDLIB.rar CPLDs the convenience of the protel into China
Category: Embeded-SCM Develop Upload User：haitiankj Size：312K
[MultiPlatform] digitalsecondwatch(VHDL).Rar use VHDL, CPLD, EDA software to design digital system, can significantly improve design flexibility, improve product performance, reduce ... the chip design is becoming electronic systems design. VHDL, CPLD/FPGA, EDA software development has become a complex ...
Category: Embeded-SCM Develop Upload User：sysmdq Size：1K
[C/C++] CPLD_used_in_AC_motor_control_system.rar
Category: Embeded-SCM Develop Upload User：gjf0302 Size：88K
[Others] LiodCPLD.rar
Category: VHDL-FPGA-Verilog Upload User：szyyn1972 Size：844K

keyword: CPLD