CPLD code resource search result, page 24, Verysource

[VHDL] FPGA_CPLDdesign.rar Described in detail the primary FPGA and CPLD portal content, e-books is a good FPGA.
Category: Embeded-SCM Develop Upload User：gogo138 Size：189K
[TEXT] hdb3decoder.rar I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
Category: VHDL-FPGA-Verilog Upload User：szwl_yx Size：117K
[MultiPlatform] inface.rar an interface to the control board CPLD logic circuit design process.
Category: VHDL-FPGA-Verilog Upload User：yaoshuwu Size：5K
[C/C++] upsd_logic.zip UPSD3200 Series MCU CPLD logic functions C51 Development Kit code!
Category: SCM Upload User：wchlt918 Size：10K
[C/C++] file_verilog.zip the documents on the CPLD, and the C language is close to that of the five counters one.
Category: VHDL-FPGA-Verilog Upload User：tychdyx Size：242K
[MultiPlatform] sopc.rar ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
Category: VHDL-FPGA-Verilog Upload User：jp61222 Size：8656K
[C/C++] low-frequencydigitalphase-measuringinstrument. ... , digital believe the shift occurred, the digital shift occurred some believe that the use of lock-in technologies, such as CPLD technology, the output waveform accuracy greatly improved, and can automatic calibration frequency, frequency stability.
Category: SCM Upload User：shenfor Size：423K
[Windows_Unix] mp3if.rar through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasions.
Category: VHDL-FPGA-Verilog Upload User：tradecn86 Size：1K
[Matlab] IODATA.zip CPLD controls R/W of DUSH. Run in LINUX. Ready to use after unzipped.
Category: Embeded-SCM Develop Upload User：youlian Size：3K
[C/C++] cpld_bus.rar CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
Category: VHDL-FPGA-Verilog Upload User：zhlf001 Size：213K

keyword: CPLD