-
-
[
Others]
MVHDL.rar
the parallel program for controlling flash ROM programs, rom flash can be read out information, After drawing CPLD controller will turn into VESA video signal and output to screen. The program has strong experience card
-
[
Visual C++ (VC++)]
LA_USB.rar
between USB and CPLD transmission, has completed testing, SRAM is about to data from USB FX2 GPIF I read, use EZ-USB Control Panel Reading
-
[
Others]
CPLD_example_50.rar
50 different functional CPLD procedures example, can be taken out, after each of the comprehensive test very useful
-
[
Others]
cpldtodds.rar
dds signal generator program design, block diagram, the CPLD based on DDS Digital Frequency Synthesizer Design
-
[
WORD]
95108325.rar
through CPLD serial communications VHDL, pretty easy to understand
-
-
[
Others]
VHDL-ysw.rar
CPLD-based time clock chess competitions, a CNT60 achieve seconds timing, CNT60 second minute of time to achieve functional, CTT3 completion of the two-hour time function. Module seconds into time- and-switch K1 phase minutes for a time module can be ...
-
[
Others]
bingxingtongxin.rar
introduces the MAX7000 Altera Corporation Series CPLD The position with SCM 04ISA bus interface between the telecommunications firms. Gives the system design and source code.
Category:
SCM Upload User：
solarhyman Size：
88K
-
[
Others]
VHDLRAM.rar
... language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
-
切换至中文 Over 1 million code package, 10 million code file free download 
