信号 code resource search result, page 60, Verysource

[C/C++] MPEG-4kaifabao(windows).rar Video capture demo source code can be MEPG-4 YYU type of signal acquisition and real-time playback of compressed
Category: Compress-Decompress algrithms Upload User：gzfyzs Size：725K
[C/C++] a2dp_source_dongle.rar Based on the agreement ADP2P source Bluetooth adapter with CSR chip, can signal via Bluetooth stereo audio launch. If the IPOD music to a stereo Bluetooth headset launched in
Category: Audio program Upload User：ax_001 Size：55K
[Visual C++ (VC++)] RecoveryofSignalfromTransientScatteredResponseCont This paper analyzes the use of empirical mode decomposition (Empirical Mode Decomposition, EMD) method to deal with non-stationary noise signals in the basic principles and methods of use of EMD effectively eliminates the Gaussian white noise on the ...
Category: Speech/Voice recognition/combine Upload User：jnyhrs Size：97K
[Visual C++ (VC++)] USANIGRIASTO97968785F16plane.rar err
Category: Windows Kernel Upload User：hebitl Size：327K
[PDF] OFDMMultiRadarProcessAndDetect.rar the paper:Signal Processing and Detecting for Multicarrier Modulated Radar System Based on OFDM
Category: Communication Upload User：ncfj119 Size：181K
[Others] dds9851sopc.rar dds signal generator, based on the 9851. more generic.
Category: Communication-Mobile Upload User：luckying_p Size：534K
[LabView] signalacquisition.rar Use of LabVIEW development of signal acquisition system, able to simulate a very good signal acquisition!
Category: OS Develop Upload User：syddz888 Size：28K
[Visual C++ (VC++)] UDP.rar windows Based on VC++ and UDP protocols data reception process, based on a transparent transfer protocol, mfc interface with receive a confirmation signal
Category: Windows Develop Upload User：any003 Size：1923K
[VHDL] jcq.rar vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0
Category: VHDL-FPGA-Verilog Upload User：lexin_2002 Size：42K
[VHDL] ls192.rar vhdl, decimal addition and subtraction counter, the output count sequence signal
Category: VHDL-FPGA-Verilog Upload User：lappkabel Size：39K

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