VHDL-FPGA-Verilog

Development Platform:

MultiPlatform

SCAN4.VHD：Code Content

							--The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity scan4 is
  port (rst,clk : in STD_LOGIC;
        a,b,c,d: in STD_LOGIC_vector(6 downto 0);
        pa,pb,pc,pd : out STD_LOGIC;
        mux_out: out STD_LOGIC_vector(6 downto 0));
end scan4;
architecture arch of scan4 is
  signal sel : std_logic_vector(1 downto 0);
begin
  process (rst,clk,A, B, C, D)
  begin
    if rst='1' then sel<="00";
    elsif rising_edge(clk) then
          sel<=sel + "01";
          case SEL is
          when "00" => MUX_OUT <= A;
                       pa<='1';pb<='0';pc<='0';pd<='0'; 
          when "01" => MUX_OUT <= B; 
                       pa<='0';pb<='1';pc<='0';pd<='0'; 
          when "10" => MUX_OUT <= C;
                       pa<='0';pb<='0';pc<='1';pd<='0'; 
          when "11" => MUX_OUT <= D;
                       pa<='0';pb<='0';pc<='0';pd<='1'; 
          when others => MUX_OUT <= "1011111";
        end case;
    end if;
  end process;
end arch;

						