VHDL-FPGA-Verilog

Development Platform:

C/C++

地址译码（for m68008）.txt：Code Content

							-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be '0' to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity addrdec is
        port(
        asbar : in std_logic; 
        address : in std_logic_vector(19 downto 0);
        csbar : out std_logic_vector(3 downto 0)
        );
end entity addrdec;
architecture v1 of addrdec is
begin
        csbar(0) <= '0' when 
                ((asbar  = '0') and 
                ((address >=  X"00000") and (address <=  X"01FFF"))) 
                else '1';
                                                                
        csbar(1) <= '0' when 
                ((asbar  = '0') and 
                ((address >=  X"40000") and (address <=  X"43FFF"))) 
                else '1';
                                                                
        csbar(2) <= '0' when 
                ((asbar  = '0') and 
                ((address >=  X"08000") and (address <=  X"0AFFF"))) 
                else '1';
                                                                
        csbar(3) <= '0' when 
                ((asbar  = '0') and 
                ((address >=  X"E0000") and (address <=  X"E01FF"))) 
                else '1';               
                                                                                                                                                                                
end architecture v1;

						