VHDL-FPGA-Verilog

Development Platform:

Windows_Unix

testmemory.v：Code Content

							module testmemory;
reg[7:0] memory[9:0];
integer index;
initial begin
  $readmemb("men.dat",memory);
  for(index=0;index<10;index=index+1)
     $display("memory[%d]=%b",index[3:0],memory[index]);
end
endmodule

						