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clk_counter_test.v
Package: verilogsourcefiles.rar　[view]
Upload User: xyledys
Upload Date: 2009-08-08
Package Size: 20k
Code Size: 0k
Category:

VHDL-FPGA-Verilog

Development Platform:

Windows_Unix

clk_counter_test.v：Code Content
  1. module clk_counter_test;
  2. wire[3:0] count_out;
  3. reg clk;
  4. clk_counter M1(count_out,clk);
  5. initial
  6.   begin
  7.     clk=0;
  8.     #10 clk=1;
  9.     #10 clk=0;
  10.     #10 clk=1;
  11.     #10 clk=0;
  12.     #10 clk=1;
  13.     #10 clk=0;
  14.     #10 clk=1;
  15.     #10 clk=0;
  16.     #10 clk=1;
  17.   end
  18. endmodule