VHDL-FPGA-Verilog

Development Platform:

Windows_Unix

timing_control_inner_mode.v：Code Content

							module timing_control_inner_mode(b,c,d,a,clk,enable);
output b,c,d;
input a,clk,enable;
reg b,c,d;
initial
  fork
    b=0;
    c=0;
    d=0;
  join
initial
  fork
    b=#5 a;
    c=@(posedge clk) a;
    wait(enable)d=a;
  join
endmodule

						