VHDL-FPGA-Verilog

Development Platform:

VHDL

clkdiv.v：Code Content

							module clkdiv(clkin,clkout);
	input clkin;
	output clkout;
	reg [31:0] cnt;
	reg clkout;
always @ (posedge clkin)
begin
	if(cnt <10000)
	begin
		cnt <= cnt + 1;
	end
	else
	begin
		cnt <= 0;
		clkout <= 1;
	end
	if(cnt == 5000)
	begin
		clkout <= 0;
	end
end
endmodule

						