VHDL-FPGA-Verilog

Development Platform:

VHDL

I8253f.fit.rpt：Code Content

; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
; Differential 1.2-V HSTL ; 0 pF ; Not Available ;
+----------------------------------+-------+------------------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; ALMs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Combinational with no register ; Register-Only ; Combinational with a register ; Full Hierarchy Name ; Library Name ;
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ALUT/register pair ; ALUT/register pair ; ALUT/register pair ; ; ;
+----------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------+--------------+
; |I8253f ; 393 (393) ; 206 (206) ; 58 (58) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 48 ; 0 ; 323 (323) ; 0 (0) ; 58 (58) ; |I8253f ; work ;
+----------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------+
; Delay Chain Summary ;
+------------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------+
; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; DQS bus ; NDQS bus ; DQS output ;
+------------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------+
; dataout[0] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; dataout[1] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; dataout[2] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; dataout[3] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; dataout[4] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; dataout[5] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; dataout[6] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; dataout[7] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; clk_out[0] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; clk_out[1] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; clk_out[2] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[0] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[1] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[2] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[3] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[4] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[5] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[6] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[7] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[8] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[9] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[10] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[11] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[12] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[13] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[14] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; cnt0[15] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; en ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;
; gate0 ; Input ; 0 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; clk0 ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; reset ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; WR ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; RD ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; CS ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; A0 ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; A1 ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; datain[1] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; datain[0] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; datain[7] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; datain[6] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; datain[5] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; datain[4] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; datain[3] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; datain[2] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;
; gate1 ; Input ; 7 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; clk1 ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; clk2 ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
; gate2 ; Input ; 7 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;
+------------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------+
+-------------------------------------------------------------+
; Pad To Core Delay Chain Fanout ;
+-------------------------------+-------------------+---------+
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
+-------------------------------+-------------------+---------+
; gate0 ; ; ;
; - all_gate0~101 ; 1 ; 7 ;
; - edge0 ; 0 ; 0 ;
; - edge0a~74 ; 1 ; 7 ;
; - reg0~30 ; 1 ; 7 ;
; - all_set0~371 ; 1 ; 7 ;
; - all_set0~372 ; 1 ; 7 ;
; - all_gate0~101DUPLICATE ; 1 ; 7 ;
; clk0 ; ; ;
; - cnt0[15]~reg0 ; 0 ; 0 ;
; - cnt0[14]~reg0 ; 0 ; 0 ;
; - cnt0[13]~reg0 ; 0 ; 0 ;
; - cnt0[12]~reg0 ; 0 ; 0 ;
; - cnt0[11]~reg0 ; 0 ; 0 ;
; - cnt0[10]~reg0 ; 0 ; 0 ;
; - cnt0[9]~reg0 ; 0 ; 0 ;
; - cnt0[8]~reg0 ; 0 ; 0 ;
; - cnt0[7]~reg0 ; 0 ; 0 ;
; - cnt0[6]~reg0 ; 0 ; 0 ;
; - cnt0[5]~reg0 ; 0 ; 0 ;
; - cnt0[4]~reg0 ; 0 ; 0 ;
; - cnt0[3]~reg0 ; 0 ; 0 ;
; - cnt0[2]~reg0 ; 0 ; 0 ;
; - cnt0[1]~reg0 ; 0 ; 0 ;
; - cnt0[0]~reg0 ; 1 ; 0 ;
; reset ; ; ;
; - all_set1~538 ; 1 ; 7 ;
; - all_set2~426 ; 1 ; 7 ;
; - all_set0~372 ; 1 ; 7 ;
; WR ; ; ;
; - Decoder0~410 ; 0 ; 0 ;
; - Decoder0~411 ; 1 ; 0 ;
; - Decoder0~412 ; 1 ; 0 ;
; - Decoder0~413 ; 1 ; 0 ;
; - Decoder0~414 ; 1 ; 0 ;
; - Decoder0~415 ; 0 ; 0 ;
; - Decoder0 ; 1 ; 0 ;
; RD ; ; ;
; - Decoder0~410 ; 1 ; 0 ;
; - Decoder0~411 ; 1 ; 0 ;
; - Decoder0~412 ; 1 ; 0 ;
; - Decoder0~413 ; 1 ; 0 ;
; - Decoder0~414 ; 1 ; 0 ;
; - Decoder0~415 ; 1 ; 0 ;
; - Decoder0 ; 1 ; 0 ;
; CS ; ; ;
; - Decoder0~410 ; 0 ; 0 ;
; - Decoder0~411 ; 1 ; 0 ;
; - Decoder0~412 ; 1 ; 0 ;
; - Decoder0~413 ; 1 ; 0 ;
; - Decoder0~414 ; 1 ; 0 ;
; - Decoder0~415 ; 0 ; 0 ;
; - Decoder0 ; 1 ; 0 ;
; A0 ; ; ;
; - Decoder0~410 ; 1 ; 0 ;
; - Decoder0~411 ; 0 ; 0 ;
; - Decoder0~412 ; 0 ; 0 ;
; - Decoder0~413 ; 0 ; 0 ;
; - Decoder0~414 ; 0 ; 0 ;
; - Decoder0~415 ; 1 ; 0 ;
; - Decoder0 ; 0 ; 0 ;
; A1 ; ; ;
; - Decoder0~410 ; 0 ; 0 ;
; - Decoder0~411 ; 0 ; 0 ;
; - Decoder0~412 ; 0 ; 0 ;
; - Decoder0~413 ; 0 ; 0 ;
; - Decoder0~414 ; 0 ; 0 ;
; - Decoder0~415 ; 0 ; 0 ;
; - Decoder0 ; 0 ; 0 ;
; datain[1] ; ; ;
; - Mux81~14 ; 0 ; 7 ;
; - Mux63~14 ; 0 ; 7 ;
; - Mux45~14 ; 0 ; 7 ;
; - set0[1] ; 0 ; 7 ;
; - set1[1] ; 0 ; 7 ;
; - set2[1] ; 0 ; 7 ;
; - cmd[1] ; 0 ; 7 ;
; datain[0] ; ; ;
; - Mux80~14 ; 0 ; 7 ;
; - Mux62~16 ; 0 ; 7 ;
; - Mux44~14 ; 0 ; 7 ;
; - set1[0] ; 0 ; 7 ;
; - set2[0] ; 0 ; 7 ;
; - set0[0] ; 0 ; 7 ;
; - cmd[0] ; 0 ; 7 ;
; datain[7] ; ; ;
; - Mux87~16 ; 1 ; 7 ;
; - Mux69~14 ; 1 ; 7 ;
; - Mux51~14 ; 1 ; 7 ;
; - set0[7] ; 1 ; 7 ;
; - set1[7] ; 1 ; 7 ;
; - set2[7] ; 1 ; 7 ;
; - cmd[7] ; 1 ; 7 ;
; datain[6] ; ; ;
; - Mux68~14 ; 0 ; 7 ;
; - Mux50~16 ; 0 ; 7 ;
; - Mux86~14 ; 0 ; 7 ;
; - set0[6] ; 0 ; 7 ;
; - set1[6] ; 0 ; 7 ;
; - set2[6] ; 0 ; 7 ;
; - cmd[6] ; 0 ; 7 ;
; datain[5] ; ; ;
; - Mux67~14 ; 1 ; 7 ;
; - Mux49~14 ; 1 ; 7 ;
; - Mux85~14 ; 1 ; 7 ;
; - set0[5] ; 1 ; 7 ;
; - set1[5] ; 1 ; 7 ;
; - set2[5] ; 1 ; 7 ;
; - cmd[5] ; 1 ; 7 ;
; datain[4] ; ; ;
; - Mux66~14 ; 1 ; 7 ;
; - Mux48~14 ; 1 ; 7 ;
; - Mux84~14 ; 1 ; 7 ;
; - set0[4] ; 1 ; 7 ;
; - set1[4] ; 1 ; 7 ;
; - set2[4] ; 1 ; 7 ;
; - cmd[4] ; 1 ; 7 ;
; datain[3] ; ; ;
; - Mux83~14 ; 0 ; 7 ;
; - Mux65~14 ; 0 ; 7 ;
; - Mux47~14 ; 0 ; 7 ;
; - set0[3] ; 0 ; 7 ;
; - set1[3] ; 0 ; 7 ;
; - set2[3] ; 0 ; 7 ;
; - cmd[3] ; 0 ; 7 ;
; datain[2] ; ; ;
; - Mux82~14 ; 0 ; 7 ;
; - Mux64~14 ; 0 ; 7 ;
; - Mux46~14 ; 0 ; 7 ;
; - set0[2] ; 0 ; 7 ;
; - set1[2] ; 0 ; 7 ;
; - set2[2] ; 0 ; 7 ;
; - cmd[2] ; 0 ; 7 ;
; gate1 ; ; ;
; - all_gate1~187 ; 0 ; 7 ;
; - edge1 ; 1 ; 0 ;
; - start1~57 ; 0 ; 7 ;
; - edge1a~57 ; 0 ; 7 ;
; - all_gate1~187DUPLICATE ; 0 ; 7 ;
; clk1 ; ; ;
; clk2 ; ; ;
; gate2 ; ; ;
; - all_gate2~340 ; 0 ; 7 ;
; - edge2 ; 1 ; 0 ;
; - all_set2~426 ; 0 ; 7 ;
; - edge2a~57 ; 0 ; 7 ;
; - start2~53 ; 0 ; 7 ;
+-------------------------------+-------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+------------------------+--------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+------------------------+--------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
; Decoder0 ; LCCOMB_X26_Y23_N2 ; 11 ; Clock, Latch enable ; no ; -- ; -- ; -- ;
; Decoder0~415 ; LCCOMB_X26_Y20_N18 ; 9 ; Latch enable ; no ; -- ; -- ; -- ;
; Mux10~83 ; LCCOMB_X27_Y19_N24 ; 8 ; Latch enable ; yes ; Global Clock ; GCLK11 ; -- ;
; Mux90~18 ; LCCOMB_X27_Y20_N6 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; WideOr0 ; LCCOMB_X26_Y23_N24 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; WideOr1 ; LCCOMB_X26_Y23_N18 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; WideOr2 ; LCCOMB_X26_Y23_N28 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; WideOr3 ; LCCOMB_X26_Y23_N26 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; WideOr5 ; LCCOMB_X26_Y23_N30 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; WideOr7~302 ; LCCOMB_X27_Y20_N2 ; 16 ; Latch enable ; yes ; Global Clock ; GCLK10 ; -- ;
; all_gate0~101DUPLICATE ; LCCOMB_X29_Y18_N22 ; 15 ; Clock enable ; no ; -- ; -- ; -- ;
; all_gate1~187DUPLICATE ; LCCOMB_X33_Y14_N6 ; 15 ; Clock enable ; no ; -- ; -- ; -- ;
; all_gate2~340 ; LCCOMB_X33_Y26_N0 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
; all_set0~372 ; LCCOMB_X29_Y18_N24 ; 16 ; Async. load ; yes ; Global Clock ; GCLK4 ; -- ;
; all_set1~535 ; LCCOMB_X30_Y16_N22 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; all_set1~538 ; LCCOMB_X33_Y14_N22 ; 16 ; Async. load ; yes ; Global Clock ; GCLK2 ; -- ;
; all_set2~424 ; LCCOMB_X25_Y20_N30 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; all_set2~426 ; LCCOMB_X33_Y26_N28 ; 16 ; Async. load ; yes ; Global Clock ; GCLK8 ; -- ;
; buffer~0 ; LCCOMB_X27_Y18_N2 ; 16 ; Latch enable ; yes ; Global Clock ; GCLK7 ; -- ;
; clk0 ; PIN_C7 ; 16 ; Clock ; no ; -- ; -- ; -- ;
; clk1 ; PIN_N20 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;
; clk2 ; PIN_M21 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ;
; cmd0[1]~0 ; LCCOMB_X27_Y20_N18 ; 5 ; Latch enable ; no ; -- ; -- ; -- ;
; cmd1[1]~0 ; LCCOMB_X26_Y20_N28 ; 5 ; Latch enable ; no ; -- ; -- ; -- ;
; cmd2[1]~0 ; LCCOMB_X27_Y20_N20 ; 5 ; Latch enable ; no ; -- ; -- ; -- ;
; edge0a ; LCCOMB_X27_Y17_N26 ; 1 ; Async. clear ; no ; -- ; -- ; -- ;
; edge1a ; LCCOMB_X29_Y16_N12 ; 1 ; Async. clear ; no ; -- ; -- ; -- ;
; edge2a ; LCCOMB_X25_Y18_N18 ; 1 ; Async. clear ; no ; -- ; -- ; -- ;
; gate0 ; PIN_A7 ; 7 ; Clock ; no ; -- ; -- ; -- ;
; gate1 ; PIN_C10 ; 5 ; Clock ; no ; -- ; -- ; -- ;
; gate2 ; PIN_E9 ; 5 ; Clock ; no ; -- ; -- ; -- ;
; reg1a ; LCCOMB_X30_Y16_N6 ; 1 ; Async. clear ; no ; -- ; -- ; -- ;
; set0[0]~159 ; LCCOMB_X27_Y19_N16 ; 8 ; Latch enable ; yes ; Global Clock ; GCLK0 ; -- ;
; set0[8]~157 ; LCCOMB_X27_Y19_N2 ; 8 ; Latch enable ; yes ; Global Clock ; GCLK9 ; -- ;
; set1[0]~152 ; LCCOMB_X27_Y16_N22 ; 8 ; Latch enable ; yes ; Global Clock ; GCLK14 ; -- ;
; set1[8]~153 ; LCCOMB_X27_Y16_N10 ; 8 ; Latch enable ; yes ; Global Clock ; GCLK6 ; -- ;
; set2[5]~152 ; LCCOMB_X27_Y23_N24 ; 8 ; Latch enable ; yes ; Global Clock ; GCLK15 ; -- ;
; set2[8]~153 ; LCCOMB_X27_Y23_N8 ; 8 ; Latch enable ; yes ; Global Clock ; GCLK13 ; -- ;
; wover0~48 ; LCCOMB_X27_Y19_N22 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; wover1~48 ; LCCOMB_X27_Y16_N18 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; wover2~48 ; LCCOMB_X27_Y23_N14 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
; wreset0 ; LCCOMB_X27_Y19_N0 ; 2 ; Async. clear ; yes ; Global Clock ; GCLK5 ; -- ;
; wreset1 ; LCCOMB_X27_Y16_N26 ; 3 ; Async. clear ; no ; -- ; -- ; -- ;
; wreset2 ; LCCOMB_X27_Y23_N30 ; 3 ; Async. clear ; no ; -- ; -- ; -- ;
; write1 ; LCCOMB_X26_Y23_N16 ; 11 ; Clock ; no ; -- ; -- ; -- ;
; write1 ; LCCOMB_X26_Y23_N16 ; 2 ; Clock, Latch enable ; yes ; Global Clock ; GCLK12 ; -- ;
; write2 ; LCCOMB_X26_Y23_N8 ; 10 ; Clock, Latch enable ; no ; -- ; -- ; -- ;
+------------------------+--------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+--------------+--------------------+---------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------+--------------------+---------+----------------------+------------------+---------------------------+
; Mux10~83 ; LCCOMB_X27_Y19_N24 ; 8 ; Global Clock ; GCLK11 ; -- ;
; WideOr7~302 ; LCCOMB_X27_Y20_N2 ; 16 ; Global Clock ; GCLK10 ; -- ;
; all_set0~372 ; LCCOMB_X29_Y18_N24 ; 16 ; Global Clock ; GCLK4 ; -- ;
; all_set1~538 ; LCCOMB_X33_Y14_N22 ; 16 ; Global Clock ; GCLK2 ; -- ;
; all_set2~426 ; LCCOMB_X33_Y26_N28 ; 16 ; Global Clock ; GCLK8 ; -- ;
; buffer~0 ; LCCOMB_X27_Y18_N2 ; 16 ; Global Clock ; GCLK7 ; -- ;
; clk1 ; PIN_N20 ; 16 ; Global Clock ; GCLK3 ; -- ;
; clk2 ; PIN_M21 ; 16 ; Global Clock ; GCLK1 ; -- ;
; set0[0]~159 ; LCCOMB_X27_Y19_N16 ; 8 ; Global Clock ; GCLK0 ; -- ;
; set0[8]~157 ; LCCOMB_X27_Y19_N2 ; 8 ; Global Clock ; GCLK9 ; -- ;
; set1[0]~152 ; LCCOMB_X27_Y16_N22 ; 8 ; Global Clock ; GCLK14 ; -- ;
; set1[8]~153 ; LCCOMB_X27_Y16_N10 ; 8 ; Global Clock ; GCLK6 ; -- ;
; set2[5]~152 ; LCCOMB_X27_Y23_N24 ; 8 ; Global Clock ; GCLK15 ; -- ;
; set2[8]~153 ; LCCOMB_X27_Y23_N8 ; 8 ; Global Clock ; GCLK13 ; -- ;
; wreset0 ; LCCOMB_X27_Y19_N0 ; 2 ; Global Clock ; GCLK5 ; -- ;
; write1 ; LCCOMB_X26_Y23_N16 ; 2 ; Global Clock ; GCLK12 ; -- ;
+--------------+--------------------+---------+----------------------+------------------+---------------------------+
+----------------------------------+
; Non-Global High Fan-Out Signals ;
+------------------------+---------+
; Name ; Fan-Out ;
+------------------------+---------+
; cmd[7] ; 21 ;
; cmd[6] ; 21 ;
; clk0 ; 16 ;
; all_gate2~340 ; 16 ;
; all_gate1~187DUPLICATE ; 15 ;
; all_gate0~101DUPLICATE ; 15 ;
; cmd0[5] ; 14 ;
; cmd1[5] ; 13 ;
; cmd2[5] ; 13 ;
; Decoder0 ; 11 ;
; cnt0[0]~reg0 ; 11 ;
; write2 ; 10 ;
; write1 ; 10 ;
; cmd1[2] ; 10 ;
; cnt1[0] ; 10 ;
; cmd1[3] ; 9 ;
; cmd0[3] ; 9 ;
; Decoder0~415 ; 9 ;
; cnt0[11]~reg0 ; 9 ;
; cnt0[10]~reg0 ; 9 ;
; cnt0[9]~reg0 ; 9 ;
; cnt0[7]~reg0 ; 9 ;
; cnt0[6]~reg0 ; 9 ;
; cnt0[5]~reg0 ; 9 ;
; cnt0[2]~reg0 ; 9 ;
; cmd[5] ; 8 ;
; cmd[4] ; 8 ;
; cmd2[3] ; 8 ;
; cmd0[2] ; 8 ;
; dataout[2]~1607 ; 8 ;
; cnt0[8]~reg0 ; 8 ;
; cnt0[4]~reg0 ; 8 ;
; cnt0[3]~reg0 ; 8 ;
; cnt0[1]~reg0 ; 8 ;
; datain[2] ; 7 ;
; datain[3] ; 7 ;
; datain[4] ; 7 ;
; datain[5] ; 7 ;
; datain[6] ; 7 ;
; datain[7] ; 7 ;
; datain[0] ; 7 ;
; datain[1] ; 7 ;
; A1 ; 7 ;
; A0 ; 7 ;
; CS ; 7 ;
; RD ; 7 ;
; WR ; 7 ;
; gate0 ; 7 ;
; cmd2[2] ; 7 ;
; cmd1[1] ; 7 ;
+------------------------+---------+
+--------------------------------------------------------------------+
; Interconnect Usage Summary ;
+-------------------------------------------+------------------------+
; Interconnect Resource Type ; Usage ;
+-------------------------------------------+------------------------+
; Block interconnects ; 735 / 51,960 ( 1 % ) ;
; C16 interconnects ; 24 / 1,680 ( 1 % ) ;
; C4 interconnects ; 515 / 38,400 ( 1 % ) ;
; DPA clocks ; 0 / 4 ( 0 % ) ;
; DQS bus muxes ; 0 / 18 ( 0 % ) ;
; DQS-18 I/O buses ; 0 / 4 ( 0 % ) ;
; DQS-4 I/O buses ; 0 / 18 ( 0 % ) ;
; DQS-9 I/O buses ; 0 / 8 ( 0 % ) ;
; Differential I/O clocks ; 0 / 32 ( 0 % ) ;
; Direct links ; 147 / 51,960 ( < 1 % ) ;
; Global clocks ; 16 / 16 ( 100 % ) ;
; Local interconnects ; 237 / 12,480 ( 2 % ) ;
; NDQS bus muxes ; 0 / 18 ( 0 % ) ;
; NDQS-18 I/O buses ; 0 / 4 ( 0 % ) ;
; NDQS-4 I/O buses ; 0 / 18 ( 0 % ) ;
; NDQS-9 I/O buses ; 0 / 8 ( 0 % ) ;
; PLL transmitter or receiver load enables ; 0 / 8 ( 0 % ) ;
; PLL transmitter or receiver synch. clocks ; 0 / 8 ( 0 % ) ;
; R24 interconnects ; 13 / 1,664 ( < 1 % ) ;
; R24/C16 interconnect drivers ; 14 / 4,160 ( < 1 % ) ;
; R4 interconnects ; 659 / 59,488 ( 1 % ) ;
; Regional clocks ; 0 / 32 ( 0 % ) ;
+-------------------------------------------+------------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 6.24) ; Number of LABs (Total = 33) ;
+--------------------------------------------+------------------------------+
; 1 ; 8 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 24 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 0.64) ; Number of LABs (Total = 33) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 4 ;
; 1 Async. load ; 6 ;
; 1 Clock ; 8 ;
; 1 Clock enable ; 3 ;
+------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 11.52) ; Number of LABs (Total = 33) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 8 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 2 ;
; 14 ; 1 ;
; 15 ; 6 ;
; 16 ; 10 ;
; 17 ; 2 ;
; 18 ; 2 ;
+----------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.30) ; Number of LABs (Total = 33) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 8 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 3 ;
; 5 ; 0 ;
; 6 ; 7 ;
; 7 ; 1 ;
; 8 ; 6 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 3 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 3 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 16.24) ; Number of LABs (Total = 33) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 6 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 3 ;
; 13 ; 0 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 16 ; 0 ;
; 17 ; 2 ;
; 18 ; 1 ;
; 19 ; 4 ;
; 20 ; 1 ;
; 21 ; 1 ;
; 22 ; 1 ;
; 23 ; 1 ;
; 24 ; 1 ;
; 25 ; 0 ;
; 26 ; 2 ;
; 27 ; 2 ;
; 28 ; 1 ;
; 29 ; 0 ;
; 30 ; 0 ;
; 31 ; 0 ;
; 32 ; 0 ;
; 33 ; 0 ;
; 34 ; 2 ;
+----------------------------------------------+------------------------------+
+------------------------------------------+
; I/O Rules Summary ;
+----------------------------------+-------+
; I/O Rules Statistic ; Total ;
+----------------------------------+-------+
; Total I/O Rules ; 31 ;
; Number of I/O Rules Passed ; 4 ;
; Number of I/O Rules Failed ; 0 ;
; Number of I/O Rules Unchecked ; 0 ;
; Number of I/O Rules Inapplicable ; 27 ;
+----------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Details ;
+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
; Inapplicable ; IO_000032 ; I/O Properties Checks for Multiple I/Os ; I/O registers and SERDES should not be used at the same XY location. ; Critical ; No I/O Registers or Differential I/O Standard assignments found. ; I/O ; ;
; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 250mA for row I/Os and 250mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 1 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
; Inapplicable ; IO_000037 ; SI Related Distance Checks ; Single-ended I/O and differential I/O should not coexist in a PLL output I/O bank. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
; Inapplicable ; IO_000038 ; SI Related SSO Limit Checks ; Single-ended outputs and High-speed LVDS should not coexist in an I/O bank. ; High ; No High-speed LVDS found. ; I/O ; ;
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
; Inapplicable ; IO_000040 ; SI Related SSO Limit Checks ; The total drive strength of single ended outputs in a DPA bank should not exceed 120mA. ; High ; No DPA found. ; I/O ; ;
+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; I/O Rules Matrix ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000032 ; IO_000033 ; IO_000034 ; IO_000037 ; IO_000038 ; IO_000042 ; IO_000040 ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 48 ; 0 ; 0 ; 48 ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Total Inapplicable ; 48 ; 48 ; 48 ; 48 ; 48 ; 0 ; 48 ; 48 ; 0 ; 0 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 48 ; 0 ; 48 ; 48 ; 48 ; 48 ; 48 ;
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; dataout[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; dataout[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; dataout[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; dataout[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; dataout[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; dataout[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; dataout[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; dataout[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; clk_out[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; clk_out[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; clk_out[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; cnt0[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; en ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; gate0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; clk0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; reset ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; WR ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; RD ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; CS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; A0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; A1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; datain[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; datain[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; datain[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; datain[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; datain[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; datain[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; datain[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; datain[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; gate1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; clk1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; clk2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
; gate2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Error detection CRC ; Off ;
; nWS, nRS, nCS, CS ; Unreserved ;
; RDYnBUSY ; Unreserved ;
; Data[7..1] ; Unreserved ;
; Data[0] ; As input tri-stated ;
; ASDO,nCSO ; Unreserved ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------------------------+
; Operating Settings and Conditions ;
+---------------------------+--------+
; Setting ; Value ;
+---------------------------+--------+
; Nominal Core Voltage ; 1.20 V ;
; Low Junction Temperature ; 0 癈 ;
; High Junction Temperature ; 85 癈 ;
+---------------------------+--------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Mon Apr 19 14:43:34 2010
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off I8253f -c I8253f
Info: Automatically selected device EP2S15F484C3 for design I8253f
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
Info: Previous placement does not exist for 485 of 485 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EP2S30F484C3 is compatible
Info: Device EP2S60F484C3 is compatible
Info: Device EP2S60F484C3ES is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
Info: Pin ~DATA0~ is reserved at location E13
Warning: No exact pin location assignment(s) for 48 pins of 48 total pins
Info: Pin dataout[0] not assigned to an exact location on the device
Info: Pin dataout[1] not assigned to an exact location on the device
Info: Pin dataout[2] not assigned to an exact location on the device
Info: Pin dataout[3] not assigned to an exact location on the device
Info: Pin dataout[4] not assigned to an exact location on the device
Info: Pin dataout[5] not assigned to an exact location on the device
Info: Pin dataout[6] not assigned to an exact location on the device
Info: Pin dataout[7] not assigned to an exact location on the device
Info: Pin clk_out[0] not assigned to an exact location on the device
Info: Pin clk_out[1] not assigned to an exact location on the device
Info: Pin clk_out[2] not assigned to an exact location on the device
Info: Pin cnt0[0] not assigned to an exact location on the device
Info: Pin cnt0[1] not assigned to an exact location on the device
Info: Pin cnt0[2] not assigned to an exact location on the device
Info: Pin cnt0[3] not assigned to an exact location on the device
Info: Pin cnt0[4] not assigned to an exact location on the device
Info: Pin cnt0[5] not assigned to an exact location on the device
Info: Pin cnt0[6] not assigned to an exact location on the device
Info: Pin cnt0[7] not assigned to an exact location on the device
Info: Pin cnt0[8] not assigned to an exact location on the device
Info: Pin cnt0[9] not assigned to an exact location on the device
Info: Pin cnt0[10] not assigned to an exact location on the device
Info: Pin cnt0[11] not assigned to an exact location on the device
Info: Pin cnt0[12] not assigned to an exact location on the device
Info: Pin cnt0[13] not assigned to an exact location on the device
Info: Pin cnt0[14] not assigned to an exact location on the device
Info: Pin cnt0[15] not assigned to an exact location on the device
Info: Pin en not assigned to an exact location on the device
Info: Pin gate0 not assigned to an exact location on the device
Info: Pin clk0 not assigned to an exact location on the device
Info: Pin reset not assigned to an exact location on the device
Info: Pin WR not assigned to an exact location on the device
Info: Pin RD not assigned to an exact location on the device
Info: Pin CS not assigned to an exact location on the device
Info: Pin A0 not assigned to an exact location on the device
Info: Pin A1 not assigned to an exact location on the device
Info: Pin datain[1] not assigned to an exact location on the device
Info: Pin datain[0] not assigned to an exact location on the device
Info: Pin datain[7] not assigned to an exact location on the device
Info: Pin datain[6] not assigned to an exact location on the device
Info: Pin datain[5] not assigned to an exact location on the device
Info: Pin datain[4] not assigned to an exact location on the device
Info: Pin datain[3] not assigned to an exact location on the device
Info: Pin datain[2] not assigned to an exact location on the device
Info: Pin gate1 not assigned to an exact location on the device
Info: Pin clk1 not assigned to an exact location on the device
Info: Pin clk2 not assigned to an exact location on the device
Info: Pin gate2 not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Automatically promoted node clk1 (placed in PIN N20 (CLK3p, Input))
Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node clk2 (placed in PIN M21 (CLK1p, Input))
Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Automatically promoted node buffer~0
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node WideOr7~302
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node cmd2[1]~0
Info: Destination node cmd1[1]~0
Info: Destination node cmd0[1]~0
Info: Automatically promoted node Mux10~83
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node set0[0]~159
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node set0[8]~157
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node wover0~48
Info: Automatically promoted node set1[0]~152
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node set1[8]~153
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node wover1~48
Info: Automatically promoted node set2[5]~152
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node set2[8]~153
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node wover2~48
Info: Automatically promoted node write1
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node wlh1[1]
Info: Destination node wlh1[0]
Info: Destination node all_set1~537
Info: Destination node all_set1~536
Info: Destination node set1[8]~153
Info: Destination node reg1a
Info: Destination node wover1~47
Info: Destination node wover1~48
Info: Destination node set1[0]~152
Info: Destination node write1
Info: Automatically promoted node all_set0~372
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node all_set1~538
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node all_set2~426
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node wreset0
Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node wreset0
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 46 (unused VREF, 3.30 VCCIO, 18 input, 28 output, 0 bidirectional)
Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available
Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 43 pins available
Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available
Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available
Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available
Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available
Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available
Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 3.914 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y19; Fanout = 4; REG Node = 'set0[3]'
Info: 2: + IC(0.502 ns) + CELL(0.418 ns) = 0.920 ns; Loc. = LAB_X26_Y18; Fanout = 2; COMB Node = 'Add6~186'
Info: 3: + IC(0.117 ns) + CELL(0.378 ns) = 1.415 ns; Loc. = LAB_X27_Y18; Fanout = 1; COMB Node = 'LessThan1~548'
Info: 4: + IC(0.348 ns) + CELL(0.053 ns) = 1.816 ns; Loc. = LAB_X27_Y18; Fanout = 1; COMB Node = 'LessThan1~549'
Info: 5: + IC(0.341 ns) + CELL(0.154 ns) = 2.311 ns; Loc. = LAB_X26_Y18; Fanout = 1; COMB Node = 'LessThan1~550'
Info: 6: + IC(0.647 ns) + CELL(0.154 ns) = 3.112 ns; Loc. = LAB_X27_Y20; Fanout = 1; COMB Node = 'LessThan1~551'
Info: 7: + IC(0.348 ns) + CELL(0.053 ns) = 3.513 ns; Loc. = LAB_X27_Y20; Fanout = 1; COMB Node = 'Mux89~85'
Info: 8: + IC(0.129 ns) + CELL(0.272 ns) = 3.914 ns; Loc. = LAB_X27_Y20; Fanout = 1; REG Node = 'clk_out[0]$latch'
Info: Total cell delay = 1.482 ns ( 37.86 % )
Info: Total interconnect delay = 2.432 ns ( 62.14 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources
Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X27_Y14 to location X40_Y27
Info: Fitter routing operations ending: elapsed time is 00:00:03
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Duplicated 2 combinational logic cells to improve design speed or routability
Info: Started post-fitting delay annotation
Warning: Found 28 output pins without output pin load capacitance assignment
Info: Pin "dataout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dataout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dataout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dataout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dataout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dataout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dataout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dataout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "clk_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "clk_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "clk_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "cnt0[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "en" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file C:/altera/72/quartus/exp3/I8253f/I8253f.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 5 warnings
Info: Allocated 220 megabytes of memory during processing
Info: Processing ended: Mon Apr 19 14:43:48 2010
Info: Elapsed time: 00:00:14
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/altera/72/quartus/exp3/I8253f/I8253f.fit.smsg.