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fj.flow.rpt
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Upload Date: 2022-08-10
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VHDL-FPGA-Verilog

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VHDL

fj.flow.rpt：Code Content
  1. Flow report for fj
  2. Thu Mar 05 01:08:10 2009
  3. Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
  6. ---------------------
  7. ; Table of Contents ;
  8. ---------------------
  9.   1. Legal Notice
  10.   2. Flow Summary
  11.   3. Flow Settings
  12.   4. Flow Non-Default Global Settings
  13.   5. Flow Elapsed Time
  14.   6. Flow Log
  18. ----------------
  19. ; Legal Notice ;
  20. ----------------
  21. Copyright (C) 1991-2007 Altera Corporation
  22. Your use of Altera Corporation's design tools, logic functions 
  23. and other software and tools, and its AMPP partner logic 
  24. functions, and any output files from any of the foregoing 
  25. (including device programming or simulation files), and any 
  26. associated documentation or information are expressly subject 
  27. to the terms and conditions of the Altera Program License 
  28. Subscription Agreement, Altera MegaCore Function License 
  29. Agreement, or other applicable license agreement, including, 
  30. without limitation, that your use is for the sole purpose of 
  31. programming logic devices manufactured by Altera and sold by 
  32. Altera or its authorized distributors.  Please refer to the 
  33. applicable agreement for further details.
  37. +--------------------------------------------------------------------------+
  38. ; Flow Summary                                                             ;
  39. +-------------------------------+------------------------------------------+
  40. ; Flow Status                   ; Successful - Thu Mar 05 01:08:10 2009    ;
  41. ; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Full Version ;
  42. ; Revision Name                 ; fj                                       ;
  43. ; Top-level Entity Name         ; fj                                       ;
  44. ; Family                        ; Stratix II                               ;
  45. ; Met timing requirements       ; Yes                                      ;
  46. ; Logic utilization             ; < 1 %                                    ;
  47. ;     Combinational ALUTs       ; 77 / 12,480 ( < 1 % )                    ;
  48. ;     Dedicated logic registers ; 52 / 12,480 ( < 1 % )                    ;
  49. ; Total registers               ; 52                                       ;
  50. ; Total pins                    ; 9 / 343 ( 3 % )                          ;
  51. ; Total virtual pins            ; 0                                        ;
  52. ; Total block memory bits       ; 0 / 419,328 ( 0 % )                      ;
  53. ; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                           ;
  54. ; Total PLLs                    ; 0 / 6 ( 0 % )                            ;
  55. ; Total DLLs                    ; 0 / 2 ( 0 % )                            ;
  56. ; Device                        ; EP2S15F484C3                             ;
  57. ; Timing Models                 ; Final                                    ;
  58. +-------------------------------+------------------------------------------+
  61. +-----------------------------------------+
  62. ; Flow Settings                           ;
  63. +-------------------+---------------------+
  64. ; Option            ; Setting             ;
  65. +-------------------+---------------------+
  66. ; Start date & time ; 03/05/2009 01:07:52 ;
  67. ; Main task         ; Compilation         ;
  68. ; Revision Name     ; fj                  ;
  69. +-------------------+---------------------+
  72. +-----------------------------------------------------------------------------------------+
  73. ; Flow Non-Default Global Settings                                                        ;
  74. +------------------------------------+---------+---------------+-------------+------------+
  75. ; Assignment Name                    ; Value   ; Default Value ; Entity Name ; Section Id ;
  76. +------------------------------------+---------+---------------+-------------+------------+
  77. ; PARTITION_COLOR                    ; 2147039 ; --            ; --          ; Top        ;
  78. ; PARTITION_NETLIST_TYPE             ; SOURCE  ; --            ; --          ; Top        ;
  79. ; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off     ; --            ; --          ; eda_palace ;
  80. +------------------------------------+---------+---------------+-------------+------------+
  83. +------------------------------------------------------------------+
  84. ; Flow Elapsed Time                                                ;
  85. +-------------------------+--------------+-------------------------+
  86. ; Module Name             ; Elapsed Time ; Average Processors Used ;
  87. +-------------------------+--------------+-------------------------+
  88. ; Analysis & Synthesis    ; 00:00:02     ; 1.0                     ;
  89. ; Fitter                  ; 00:00:05     ; 1.0                     ;
  90. ; Assembler               ; 00:00:06     ; 1.0                     ;
  91. ; Classic Timing Analyzer ; 00:00:01     ; 1.0                     ;
  92. ; Total                   ; 00:00:14     ; --                      ;
  93. +-------------------------+--------------+-------------------------+
  96. ------------
  97. ; Flow Log ;
  98. ------------
  99. quartus_map --read_settings_files=on --write_settings_files=off fj -c fj
  100. quartus_fit --read_settings_files=off --write_settings_files=off fj -c fj
  101. quartus_asm --read_settings_files=off --write_settings_files=off fj -c fj
  102. quartus_tan --read_settings_files=off --write_settings_files=off fj -c fj --timing_analysis_only