Category

Development Platform
Home > SourceCode/Document > Embeded-SCM Develop > VHDL-FPGA-Verilog > View Code
count23.hier_info
Package: count23.rar　[view]
Upload User: sh57280931
Upload Date: 2022-08-10
Package Size: 285k
Code Size: 1k
Category:

VHDL-FPGA-Verilog

Development Platform:

VHDL

count23.hier_info：Code Content
  1. |count23
  2. ck => count[7].CLK
  3. ck => count[6].CLK
  4. ck => count[5].CLK
  5. ck => count[4].CLK
  6. ck => count[3].CLK
  7. ck => count[2].CLK
  8. ck => count[1].CLK
  9. ck => count[0].CLK
  10. count23[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
  11. count23[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
  12. count23[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE
  13. count23[3] <= count[3].DB_MAX_OUTPUT_PORT_TYPE
  14. count23[4] <= count[4].DB_MAX_OUTPUT_PORT_TYPE
  15. count23[5] <= count[5].DB_MAX_OUTPUT_PORT_TYPE
  16. count23[6] <= count[6].DB_MAX_OUTPUT_PORT_TYPE
  17. count23[7] <= count[7].DB_MAX_OUTPUT_PORT_TYPE