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testbench_isim_beh.wfs
Package: tutorial1.zip　[view]
Upload User: baiyl2008
Upload Date: 2022-06-25
Package Size: 360k
Code Size: 1k
Category:

VHDL-FPGA-Verilog

Development Platform:

VHDL

testbench_isim_beh.wfs：Code Content
  1. version 3
  10. 0
  15. CLOCK_LIST_BEGIN
  16. CLOCK_LIST_END
  17. SIGNAL_LIST_BEGIN
  18. SIGNAL_LIST_END
  19. SIGNALS_NOT_ON_DISPLAY
  20. SIGNALS_NOT_ON_DISPLAY_END
  21. MARKER_LIST_BEGIN
  22. MARKER_LIST_END
  23. MEASURE_LIST_BEGIN
  24. MEASURE_LIST_END
  25. SIGNAL_ORDER_BEGIN
  26. /testbench/a
  27. /testbench/b
  28. /testbench/c
  29. /testbench/d
  30. /testbench/y
  31. SIGNAL_ORDER_END
  32. DIFFERENTIAL_CLKS_BEGIN
  33. DIFFERENTIAL_CLKS_END
  34. DIVIDERS_BEGIN
  35. DIVIDERS_END
  36. SIGPROPS_BEGIN
  37. /testbench/a
  38. 2
  39. 0
  40. /testbench/b
  41. 2
  42. 0
  43. /testbench/c
  44. 2
  45. 0
  46. /testbench/d
  47. 2
  48. 0
  49. /testbench/y
  50. 2
  51. 0
  52. SIGPROPS_END
  53. GROUPS_HIER_BEGIN
  54. GROUPS_HIER_END
  55. GROUPS_CHILDREN_BEGIN
  56. GROUPS_CHILDREN_END