Compress-Decompress algrithms

Development Platform:

VHDL

pe1.v：Code Content

							module pe1(new_ina,new_inb,rb_in,pin,cbin,clk,sela,selb,
          new_outa,new_outb,rb_out,pout,cbout,en_cb,en_new);
input [7:0] new_ina,new_inb,rb_in,pin,cbin;
input clk;
input sela;
input [1:0] selb;
input en_cb,en_new;
output [7:0] new_outa,new_outb,rb_out,pout,cbout;
//output [7:0] sad;
reg [7:0] sdba,sdbb,pr,rbr,cbr;
assign new_outa=sdba;
assign new_outb=sdbb;
assign rb_out=rbr;
assign pout=pr;
assign cbout=cbr;
always @ (posedge clk)
	if(en_new)
		begin
			sdba<=new_ina;
			sdbb<=new_inb;
			pr<=pin;
		end
		
always @ (posedge clk)
	case(selb)
	
		2'b01: rbr<=rb_in;
		2'b10: rbr<=sdba;
		2'b11: rbr<=sdbb;
	endcase
always @ (posedge clk)
	if (en_cb)
		begin
			if(sela)
				cbr<=cbin;
			else cbr<=pr;
		end
endmodule

						