Compress-Decompress algrithms

Development Platform:

VHDL

inter.v：Code Content

							module inter(a,en,b,clk);
input clk;
input en;
input [7:0] a;
output [7:0] b;
reg [7:0] b;
always @ (posedge clk)
		if(en)
		  b<=a;
		
endmodule

						