Category

Development Platform
Home > SourceCode/Document > Compress-Decompress algrithms > View Code
cbram_access.v
Package: inter_prediction(verilog).rar　[view]
Upload User: abszbd2002
Upload Date: 2020-10-12
Package Size: 33407k
Code Size: 4k
Category:

Compress-Decompress algrithms

Development Platform:

VHDL

cbram_access.v：Code Content
  1. //Design  :  inter prediction
  2. //Author  :  li haibin
  3. //files   :  cbram_access
  4. //Description : 当前亮度宏块ram的读写管理
  5. //---------------------------------------------------------------------------------------------------
  6. module cbram_access(clk,reset,cb_rden,cb_wren,
  7. data0,data1,data2,data3,data4,data5,data6,data7,data8,data9,
  8. data10,data11,data12,data13,data14,data15,
  9. q0,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15);
  11. input clk;
  12. input reset;
  13. input cb_rden;
  14. input cb_wren;
  15. input [7:0] data0,data1,data2,data3,data4,data5,data6,data7,data8,data9,
  16. data10,data11,data12,data13,data14,data15;
  17. output [7:0] q0,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15;
  19. reg [3:0] rdaddr;
  20. reg [3:0] wraddr;
  21. //--------------当前块ram读地址的产生
  22. always @ (posedge clk or posedge reset)
  23. if (reset==1'b1)
  24. rdaddr <= 4'b0;
  25. else
  26. if (cb_rden==1'b1)
  27. rdaddr <= rdaddr + 1'b1;
  28. else
  29. rdaddr <= 4'b0;
  30. //--------------当前块ram写地址的产生
  31. always @ (posedge clk or posedge reset)
  32. if (reset==1'b1)
  33. wraddr <= 4'b0;
  34. else
  35. if (cb_wren==1'b1)
  36. wraddr <= wraddr + 1'b1;
  37. else
  38. wraddr <= 4'b0;
  39. //--------------16个8位宽的ram组成亮度数据块
  40. cbramx cbram0(//.aclr(reset),
  41.  .clock(clk),
  42.  .data(data0),
  43.  .rdaddress(rdaddr),
  44.  .rden(cb_rden),
  45.  .wraddress(wraddr),
  46.  .wren(cb_wren),
  47.  .q(q0)
  48. );
  50. cbramx cbram1(//.aclr(reset),
  51.  .clock(clk),
  52.  .data(data1),
  53.  .rdaddress(rdaddr),
  54.  .rden(cb_rden),
  55.  .wraddress(wraddr),
  56.  .wren(cb_wren),
  57.  .q(q1)
  58. );
  59. cbramx cbram2(//.aclr(reset),
  60.  .clock(clk),
  61.  .data(data2),
  62.  .rdaddress(rdaddr),
  63.  .rden(cb_rden),
  64.  .wraddress(wraddr),
  65.  .wren(cb_wren),
  66.  .q(q2)
  67. );
  68. cbramx cbram3(//.aclr(reset),
  69.  .clock(clk),
  70.  .data(data3),
  71.  .rdaddress(rdaddr),
  72.  .rden(cb_rden),
  73.  .wraddress(wraddr),
  74.  .wren(cb_wren),
  75.  .q(q3)
  76. );
  77. cbramx cbram4(//.aclr(reset),
  78.  .clock(clk),
  79.  .data(data4),
  80.  .rdaddress(rdaddr),
  81.  .rden(cb_rden),
  82.  .wraddress(wraddr),
  83.  .wren(cb_wren),
  84.  .q(q4)
  85. );
  86. cbramx cbram5(//.aclr(reset),
  87.  .clock(clk),
  88.  .data(data5),
  89.  .rdaddress(rdaddr),
  90.  .rden(cb_rden),
  91.  .wraddress(wraddr),
  92.  .wren(cb_wren),
  93.  .q(q5)
  94. );
  95. cbramx cbram6(//.aclr(reset),
  96.  .clock(clk),
  97.  .data(data6),
  98.  .rdaddress(rdaddr),
  99.  .rden(cb_rden),
  100.  .wraddress(wraddr),
  101.  .wren(cb_wren),
  102.  .q(q6)
  103. );
  104. cbramx cbram7(//.aclr(reset),
  105.  .clock(clk),
  106.  .data(data7),
  107.  .rdaddress(rdaddr),
  108.  .rden(cb_rden),
  109.  .wraddress(wraddr),
  110.  .wren(cb_wren),
  111.  .q(q7)
  112. );
  113. cbramx cbram8(//.aclr(reset),
  114.  .clock(clk),
  115.  .data(data8),
  116.  .rdaddress(rdaddr),
  117.  .rden(cb_rden),
  118.  .wraddress(wraddr),
  119.  .wren(cb_wren),
  120.  .q(q8)
  121. );
  122. cbramx cbram9(//.aclr(reset),
  123.  .clock(clk),
  124.  .data(data9),
  125.  .rdaddress(rdaddr),
  126.  .rden(cb_rden),
  127.  .wraddress(wraddr),
  128.  .wren(cb_wren),
  129.  .q(q9)
  130. );
  131. cbramx cbram10(//.aclr(reset),
  132.  .clock(clk),
  133.  .data(data10),
  134.  .rdaddress(rdaddr),
  135.  .rden(cb_rden),
  136.  .wraddress(wraddr),
  137.  .wren(cb_wren),
  138.  .q(q10)
  139. );
  140. cbramx cbram11(//.aclr(reset),
  141.  .clock(clk),
  142.  .data(data11),
  143.  .rdaddress(rdaddr),
  144.  .rden(cb_rden),
  145.  .wraddress(wraddr),
  146.  .wren(cb_wren),
  147.  .q(q11)
  148. );
  149. cbramx cbram12(//.aclr(reset),
  150.  .clock(clk),
  151.  .data(data12),
  152.  .rdaddress(rdaddr),
  153.  .rden(cb_rden),
  154.  .wraddress(wraddr),
  155.  .wren(cb_wren),
  156.  .q(q12)
  157. );
  158. cbramx cbram13(//.aclr(reset),
  159.  .clock(clk),
  160.  .data(data13),
  161.  .rdaddress(rdaddr),
  162.  .rden(cb_rden),
  163.  .wraddress(wraddr),
  164.  .wren(cb_wren),
  165.  .q(q13)
  166. );
  167. cbramx cbram14(//.aclr(reset),
  168.  .clock(clk),
  169.  .data(data14),
  170.  .rdaddress(rdaddr),
  171.  .rden(cb_rden),
  172.  .wraddress(wraddr),
  173.  .wren(cb_wren),
  174.  .q(q14)
  175. );
  176. cbramx cbram15(//.aclr(reset),
  177.  .clock(clk),
  178.  .data(data15),
  179.  .rdaddress(rdaddr),
  180.  .rden(cb_rden),
  181.  .wraddress(wraddr),
  182.  .wren(cb_wren),
  183.  .q(q15)
  184. );
  185. endmodule