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test2.v
Package: inter_prediction(verilog).rar [view]
Upload User: abszbd2002
Upload Date: 2020-10-12
Package Size: 33407k
Code Size: 0k
Category:
Compress-Decompress algrithms
Development Platform:
VHDL
- module test2(a,b,c);
- input a;
- input b;
- output c;
- assign c=a|b;
- endmodule
