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swram48.bsf
Package: inter_prediction(verilog).rar [view]
Upload User: abszbd2002
Upload Date: 2020-10-12
Package Size: 33407k
Code Size: 6k
Category:
Compress-Decompress algrithms
Development Platform:
VHDL
- /*
- WARNING: Do NOT edit the input and output ports in this file in a text
- editor if you plan to continue editing the block that represents it in
- the Block Editor! File corruption is VERY likely to occur.
- */
- /*
- Copyright (C) 1991-2007 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- */
- (header "symbol" (version "1.1"))
- (symbol
- (rect 0 0 256 160)
- (text "swram48" (rect 102 1 163 17)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 144 25 156)(font "Arial" ))
- (port
- (pt 0 32)
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- (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
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- (text "q[7..0]" (rect 223 75 253 88)(font "Arial" (font_size 8)))
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- (text "RAM" (rect 149 58 161 78)(font "Arial" )(vertical))
- (text "Block Type: M4K" (rect 41 140 112 152)(font "Arial" ))
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